基于FPGA的ASK信号调制

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DDS IP核使用 

 下图频率计算值是:

所得的信号频率/输入的时钟频率*2^16(第一张图中的phase width值)算出来的二进制

程序

 

module top(
    input                  clk      ,
    input                  rstn     ,
    input                  send_En  ,
    input       [7:0]      send_Data,
    output      [15:0]     dout_Data,
    output reg             busy     ,
    output reg  [15:0]     dout_ASK 
);
wire        m_axis_data_tvalid;
wire [31:0] m_axis_data_tdata ;
assign dout_Data = m_axis_data_tdata[31:16];//正弦信号
//reg       busy ;
dds_compiler_0 SIN_500k (
	.aclk              (clk               ),  // input wire aclk   50M
	.aclken            (busy              ),                          // input wire aclken
	.m_axis_data_tvalid(m_axis_data_tvalid),  // output wire m_axis_data_tvalid
	.m_axis_data_tdata (m_axis_data_tdata )   // output wire [31 : 0] m_axis_data_tdata
);

reg [3:0] state;
reg       flag ;
reg [9:0] flag_d;
always@(posedge clk or negedge rstn)
	begin
		if(!rstn)begin
			busy <= 0;
		end else if(send_En)begin//发送一个字节忙状态
			busy <= 1;
		end else if(state == 7 && flag_d[4])begin
			busy <= 0;
		end
	end
reg [9:0] cnt1;
parameter num1 = 199;
always@(posedge clk or negedge rstn)
	begin
		if(!rstn)begin
			cnt1 <= 0;
		end else if(busy)begin
			if(cnt1 < num1)begin//一个bit保持时长
				cnt1 <= cnt1+1;
			end else begin
				cnt1 <= 0;
			end
		end else begin
			cnt1 <= 0;
		end
	end
always@(posedge clk or negedge rstn)
	begin
		if(!rstn)begin
			flag <= 0;
		end else if(cnt1 == num1)begin//一个bit位信号
			flag <= 1;
		end else begin
			flag <= 0;
		end
	end
always@(posedge clk)
    flag_d <= {flag_d[8:0],flag};//DDS IP信号出来信号延时，保证波形对齐
always@(posedge clk or negedge rstn)
	begin
		if(!rstn)begin
			state <= 0;
		end else if(busy)begin
			if(flag_d[4])begin
				state <= state+1;
			end else begin
				state <= state;
			end 
		end else begin
			state <= 0;
		end
	end
reg [7:0] reg_Data;
always@(posedge clk or negedge rstn)
	begin
		if(!rstn)begin
			reg_Data <= 0;
		end else if(send_En)begin//寄存待发送值
			reg_Data <= send_Data;
		end 
	end
always@(posedge clk or negedge rstn)
	begin
		if(!rstn)begin
			dout_ASK <= 0;
		end else if(busy)begin
			if(reg_Data[state])begin//波形发送
				dout_ASK <= dout_Data;
			end else begin
				dout_ASK <= 0;
			end
		end else begin
			dout_ASK <= 0;
		end
	end
endmodule

仿真图