纯Verilog实现FIFO用于3X3卷积行缓存

`timescale 1ns/1ps
module fifo#(
    parameter DATA_WIDTH = 8,
    parameter DATA_DEPTH = 1920
)
(
    input  wire                         i_clk,
    input  wire                         i_rstn,

    input  wire                         wr_en,
    input  wire [DATA_WIDTH - 1 : 0]    wr_data,
    output wire                         wr_full,

    input  wire                         rd_en,

    output wire                         rd_empty,
    output reg [DATA_WIDTH - 1 : 0]    rd_data
);

//define ram
(*ram_style = "block" *) reg [DATA_WIDTH - 1 : 0] fifo_buffer [DATA_DEPTH - 1 : 0];

integer i;

initial begin
    for(i=0;i<DATA_WIDTH;i=i+1) begin
        fifo_buffer[i] <= 0;
    end
end

reg     [$clog2(DATA_DEPTH) - 1 : 0]    wr_pointer = 0;//form end to read data
reg     [$clog2(DATA_DEPTH) - 1 : 0]    rd_pointer = 0;
reg    [DATA_WIDTH - 1 : 0]            rd_data_out;

always @(posedge i_clk or negedge i_rstn) begin
    if(!i_rstn) begin
        wr_pointer <= 0;
    end
    else begin
        if(wr_en) begin
            if(wr_pointer == DATA_DEPTH - 1) begin
                wr_pointer <= 0;
            end
            else begin
                wr_pointer <= wr_pointer + 1'd1;
            end
        end
        else begin
            wr_pointer <= 0;
        end
    end
end

always @(posedge i_clk or negedge i_rstn) begin
    if(!i_rstn) begin
        rd_pointer <= 0;
    end
    else begin
        if(rd_en) begin
            if(rd_pointer == DATA_DEPTH - 1) begin
                rd_pointer <= 0;
            end
            else begin
                rd_pointer <= rd_pointer + 1'd1;
            end
        end
        else begin
            rd_pointer <= 0;
        end
    end
end

always @(posedge i_clk or negedge i_rstn) begin
    if(!i_rstn) begin
        fifo_buffer[wr_pointer] <= 0;
    end
    else begin
        if(wr_en) begin
            fifo_buffer[wr_pointer] <= wr_data;
        end
        else begin
            fifo_buffer[wr_pointer] <= fifo_buffer[wr_pointer];
        end
    end
end

always @(posedge i_clk or negedge i_rstn) begin
    if(!i_rstn) begin
        rd_data_out <= 0;
    end
    else begin
        if(rd_en) begin
            rd_data_out <= fifo_buffer[wr_pointer];
        end
        else begin
            rd_data_out <= 0;
        end
    end
end

always @(posedge i_clk or negedge i_rstn) begin
    if(!i_rstn) begin
        rd_data <= 0;
    end
    else begin
        rd_data <= rd_data_out;
    end
end
endmodule