fpga8状态循环LED灯

module counter_led_6(
    Clk,
    Reset_n,
    Ctrl,
    Time,
    Led
 );
    
    input Clk;
    input Reset_n;
    input  [7:0]Ctrl;
    input [31:0]Time;
    output reg Led;
    
    reg [18:0]counter0;
    reg [31:0]counter;
    reg [2:0]counter2;
    
    parameter MCNT = 5000000;
    
    always@( posedge Clk or negedge Reset_n)
    if (!Reset_n)
        counter0 <= 0;
    else if ( counter0 == MCNT-1 )
        counter0 <= 0;
    else
        counter0 = counter0 + 1;
    
    
    reg EN;
    always@( posedge Clk or negedge Reset_n)
    if (!Reset_n)
        EN <= 0;
    else if (  counter0 ==  0  )//else if (  counter0 ==  MCNT-1 )仿真有误，下板无误，很奇怪
        EN <= 1;
    else if (( counter2 == 7) && ( counter == Time-1 ))//避免竞争
        EN <= 0;
    else
        EN <= EN;
    
    always@( posedge Clk or negedge Reset_n)
    if (!Reset_n)
        counter <= 0;
    else if( EN == 1 )begin
        if ( counter == Time-1 )
            counter <= 0;
        else
            counter <= counter + 1;
    end
    else
        counter <= 0;
        
    always@( posedge Clk or negedge Reset_n)
    if (!Reset_n)
        counter2 <= 0;
    else if( EN == 1 )begin
        if ( counter == Time-1 )
            counter2 <= counter2 + 1;
        else
            counter2 <= counter2;
    end
    else
        counter2 <= 0;
    

    always@( posedge Clk or negedge Reset_n)
    if (!Reset_n)
        Led <= 1;
    else  
        case ( counter2 )
            0: Led <= Ctrl[0];
            1: Led <= Ctrl[1];
            2: Led <= Ctrl[2];
            3: Led <= Ctrl[3];
            4: Led <= Ctrl[4];
            5: Led <= Ctrl[5];
            6: Led <= Ctrl[6];
            7: Led <= Ctrl[7];
            default : Led <= Led;
endcase

    
endmodule