HDLBits练习——Fsm1s

This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.

This exercise is the same as fsm1, but using synchronous reset.

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前言

三个输入，包括一个时钟clk，一个高电平有效的同步置位信号reset，一个输入信号in；一个输出信号out。

代码

module top_module(clk, reset, in, out);
    input clk;
    input reset;   
    input in;
    output out;
    reg out;
    parameter A=0,B=1;
    reg state, next_state;
    
    always@(*)begin
        if(state==A) next_state=in?A:B;
        else next_state=in?B:A;
    end
    
    always@(posedge clk)begin        
        if(reset) state<=B;
        else state<=next_state;
    end
    
    assign out=state;
               
endmodule

总结

三段式真的YYDS，写起来清晰明了，而且易读易理解，棒极了！