Verilog刷题HDLBits——Fsm1s

题目描述

This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.

This exercise is the same as fsm1, but using synchronous reset.

代码

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  
    reg out;

    // Fill in state name declarations
    parameter A=0,B=1;

    reg present_state, next_state;

    always @(posedge clk) begin
        if (reset) begin  
            // Fill in reset logic
            next_state=B;
        end else begin
            case (present_state)
                // Fill in state transition logic
                A: if(in==1)
                    next_state=A;
                	else
                        next_state=B;
                B: if(in==1)
                    next_state=B;
                	else
                        next_state=A;
            endcase
        end
            // State flip-flops
            present_state = next_state;   

            case (present_state)
                // Fill in output logic
                A: out=1'b0;
                B: out=1'b1;
            endcase
    end

endmodule

结果