load_syn_ff (
input clk ,
input rst_n ,
input in,
input out ,
input load,
output out
);
always @(posedge clk) begin
if(!rst_n)
out <= 1'd0 ;
else if (load)
out <= in ;
end
load_asyn_ff (
input clk ,
input rst_n ,
input in,
input out ,
input load,
output out
);
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
out <= 1'd0 ;
else if (load)
out <= in ;
end
always @(posedge clk or negedge rst_async_n) begin
if(!rst_async_n) begin
rst_n0 <= 1'b0;
rst_n1 <= 1'b0;
end
else begin //同步釋放
rst_n0 <= rst_n ;
rst_n1 <= rst_n0 ;
end
end
assign rst_sync_n = rst_n1;