[HDLBits] Lfsr32

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最新推荐文章于 2024-03-18 10:31:49 发布

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分类专栏： HDLBits 文章标签： fpga开发 fpga verilog

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See Lfsr5 for explanations.

Build a 32-bit Galois LFSR with taps at bit positions 32, 22, 2, and 1.

module top_module(
    input clk,
    input reset,    // Active-high synchronous reset to 32'h1
    output [31:0] q
); 

    always@(posedge clk)begin
        if(reset)
            q <= 32'h1;
        else begin
            {q[30:22],q[20:2]} <= {q[31:23],q[21:3]};
            q[31] <= q[0]^1'b0;
            q[21] <= q[0]^q[22];
            q[1] <= q[0]^q[2];
            q[0] <= q[0]^q[1];
        end
    end
endmodule