利用EDA编程软件实现选择器的构造（vhdl）

1.二选一选择器

（1）代码

VHDL程序

library IEEE;

use ieee.std_logic_1164.all;

entity xuanzeqi is

    port(a,b,s:in std_logic;

             y: out std_logic );

end entity xuanzeqi;

architecture one of xuanzeqi is

begin

   process(a,b,s)

   begin

       if s='0' then y<=a;

       else y<=b;

     end if;

  end process;

 end architecture one;

（2）波形图

2.四选一选择器

(1)代码

library IEEE;
use ieee.std_logic_1164.all;

entity sixuanyi is
    port(s: in std_logic_vector(1 downto 0);
             a,b,c,d: in std_logic; 
             y: out std_logic );
end sixuanyi;
architecture one of sixuanyi is
begin
   process(s)
   begin
     If s="00" then y<=a;
     Elsif s="01" then y<=b;
     Elsif s="10" then y<=c;
     Elsif s="11" then y<=d;
     else null;
     end if;
  end process;
 end architecture one;

（2）波形