6–2 Parallel Binary Adders

After completing this section, you should be able to

u Use full-adders to implement a parallel binary adder

u Explain the addition process in a parallel binary adder

u Use the truth table for a 4-bit parallel adder

u Apply two 74HC283s for the addition of two 8-bit numbers

u Expand the 4-bit adder to accommodate 8-bit or 16-bit addition

a single full-adder is capable of adding two 1-bit numbers and an input carry.

When one binary number is added to another, each column generates a sum bit and a 1 or 0 carry bit to the next column to the left, as illustrated here with 2-bit numbers

 So for 2-bit numbers, two adders are needed; for 4-bit numbers, four adders are used; and so on.

 Four-Bit Parallel Adders

A group of four bits is called a nibble.

 

 

Adder Expansion

This process is known as cascading 串联. Notice that, in this case, the output carry is designated C8 because it is generated from the eighth bit position.

 

An Application 

 The resistors from the inputs of each full-adder to ground assure that each input is LOW when the switch is in the neutral position (CMOS logic is used). When a switch is moved to the “yes” or to the “no” position, a HIGH level (VCC) is applied to the associated full adder input