6–10 Parity Generators/Checkers

Errors can occur as digital codes are being transferred from one point to another within a digital system or while codes are being transmitted from one system to another. The errors take the form of undesired changes in the bits that make up the coded information; that is, a 1 can change to a 0, or a 0 to a 1, because of component malfunctions or electrical noise. In most digital systems, the probability that even a single bit error will occur is very small, and the likelihood that more than one will occur is even smaller. Nevertheless, when an error occurs undetected, it can cause serious problems in a digital system. After completing this section, you should be able to u Explain the concept of parity u Implement a basic parity circuit with exclusive-OR gates u Describe the operation of basic parity generating and checking logic u Discuss the 74HC280 9-bit parity generator/checker u Use VHDL to describe a 9-bit parity generator/checker u Discuss how error detection can be implemented in a data transmission system The parity method of error detection in which a parity bit is attached to a group of information bits in order to make the total number of 1s either even or odd (depending on the system) was covered in Chapter 2. In addition to parity bits, several specific codes also provide inherent error detection

在数字系统中，当数字代码从系统的一个点传输到另一个点，或者当代码从一个系统传输到另一个系统时，可能会发生错误。这些错误表现为编码信息中位的非预期改变；也就是说，一个1可能由于组件故障或电气噪声而变成0，或者0变成1。在大多数数字系统中，即使发生单个位错误的概率也非常小，发生多个位错误的可能性甚至更小。然而，当一个错误发生但未被检测到时，它可能会在数字系统中造成严重问题。

完成本节后，您应该能够：

- 解释奇偶校验的概念
- 使用异或门实现基本奇偶校验电路
- 描述基本奇偶校验生成和检验逻辑的操作
- 讨论74HC280 9位奇偶校验生成器/检验器
- 使用VHDL描述一个9位奇偶校验生成器/检验器
- 讨论如何在数据传输系统中实现错误检测

在第2章中已经介绍了一种奇偶校验的错误检测方法，即在一组信息位上附加一个奇偶校验位，以使总的1的数量为偶数或奇数（取决于系统）。除了奇偶校验位外，还有几种特定的编码方式也提供了固有的错误检测功能。

Basic Parity Logic

In order to check for or to generate the proper parity in a given code, a basic principle can be used:

The sum (disregarding carries) of an even number of 1s is always 0, and the sum of an odd number of 1s is always 1.

Therefore, to determine if a given code has even parity or odd parity, all the bits in that code are summed. As you know, the modulo-2 sum of two bits can be generated by an exclusive-OR gate, as shown in Figure 6–55(a); the modulo-2 sum of four bits can be formed by three exclusive-OR gates connected as shown in Figure 6–55(b); and so on. When the number of 1s on the inputs is even, the output X is 0 (LOW). When the number of 1s is odd, the output X is 1 (HIGH).

 

 

 A Data Transmission System with Error Detection

奇偶校验器的作用是检查数据的奇偶性，以确定数据中是否存在错误。在分解复用器系统中，奇偶校验器用于检查从多路复用器传输的数据流的奇偶性。当所有数据位都被传输并存储在奇偶校验器中后，奇偶校验器会对数据进行校验。如果数据中存在错误（即校验位与数据位的奇偶性不匹配），则奇偶校验器会输出一个错误信号，指示数据中存在错误。这种方法可以帮助检测传输过程中可能发生的错误，提高数据传输的可靠性。