1.S and R
2. Gated S-R
3. Gated D Latch
4. The D Flip-Flop
5.The J-K Flip-Flop
6. D Flip-Flop Edge triggering.
7.J-K Flip-Flop Edge triggering.
8. Asynchronous Preset and Clear Inputs
9. Implementation: J-K Flip-Flop
7–3 Flip-Flop Operating Characteristics
1.Propagation Delay Times
2.Set-up Time
3.Hold Time
4.Maximum Clock Frequency
The maximum clock frequency (fmax) is the highest rate at which a flip-flop can be reliably triggered. At clock frequencies above the maximum, the flip-flop would be unable to respond quickly enough, and its operation would be impaired.
5.Pulse Widths
Minimum pulse widths (tW) for reliable operation are usually specified by the manufacturer for the clock, preset, and clear inputs. Typically, the clock is specified by its minimum HIGH time and its minimum LOW time
6.Power Dissipation
7–4 Flip-Flop Applications
1.Parallel Data Storage
2.Frequency Division
3.Counting
7–5 One-Shots
2. Nonretriggerable One-Shot
在这里,“provisions”是指集成电路(IC)74121提供了外部R(电阻)和C(电容)连接的可能性。这个词通常在技术文档中用来指“提供”或“预备”,在这个上下文中,它意味着这个IC设计上允许用户连接外部的电阻和电容,这样可以让用户根据需求设定时间参数。这些外部组件用来影响IC的触发时间特性。