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MasterZLee
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二位十进制计数器 Verilog-modelsim
##tb.v (tb)`timescale 1ns/100ps module tb; reg clk, rst; wire [7:0] dout; initial begin clk = 1'b0; forever #5 clk = ~clk; end initial begin ...原创 2020-01-11 12:58:17 · 6152 阅读 · 0 评论 -
二选一多路选择器 Verilog-modelsim
##tb.v (tb)`timescale 1ns/100ps module tb; reg ain, bin; reg select; initial begin ain = 1'b0; forever #5 ain = ~ain; end initial begin ...原创 2020-01-11 12:53:51 · 3832 阅读 · 0 评论 -
全加器 Verilog-modelsim
##tb.v (tb)`timescale 1ns/100ps module tb; reg ain, bin; reg cin; initial begin ain = 1'b0; forever #5 ain = ~ain; end initial begin ...原创 2020-01-11 12:47:25 · 1660 阅读 · 0 评论 -
8-3优先编码器 Verilog-modelsim
#8-3优先编码器 Verilog-modelsim##tb.v (tb)`timescale 1ns/1ns module tb; reg [7:0] din; wire [2:0] dout; initial begin din = 8'b00000000 ; forever #5 din...原创 2020-01-11 12:41:06 · 9649 阅读 · 1 评论