##tb.v (tb)
`timescale 1ns/100ps
module tb;
reg ain, bin;
reg cin;
initial begin
ain = 1'b0;
forever #5 ain = ~ain;
end
initial begin
bin = 1'b0;
forever #2.5 bin = ~bin;
end
initial begin
cin = 1'b0;
forever #20 cin = ~cin;
end
full_adder
dut
( .ain (ain ), .bin (bin ), .cin (cin ), .sum (sum ), .cout (cout ) );
always @ (cout)
begin
$display("ain = %x", ain);
$display("bin = %x", bin);
$display("cin = %x", cin);
end
endmodule
##test.do (sim)
# step 1
vlib work
# step 2
vlog ../rtl/fulladder.v
vlog ../tb/tb.v
#step 3
vsim tb
##fulladder.v (rtl)
module full_adder
(
input wire ain,bin,