二选一多路选择器 Verilog-modelsim

##tb.v (tb)

`timescale 1ns/100ps	
module tb;          
  reg ain, bin;   
  reg select;

  initial begin
  	           ain = 1'b0;
      forever #5 ain = ~ain;	
  end
  initial begin								 
  	             bin = 1'b0;   
     forever #2.5 bin = ~bin;	 
       end   
  initial begin
  	              select = 1'b0;   
     forever #10  select = ~select;
  end 												 

MUX21							
    dut
    (  .ain       (ain  ),
       .bin       (bin  ),
       .select    (select  ),
       .out       (out  )      );
    											
endmodule												

##test.do (sim)

# step 1
vlib work

# step 2
vlog ../rtl/MUX21.v
vlog ../tb/tb.v

#step 3
vsim tb

##8MUX21.v (rtl)

module MUX21
( 
		input  wire ain,bin,select,
		output reg  out
);
//常见错误case中没有default定义未定义状态，阻塞性赋值非阻塞性赋值
always @( * )
	begin
		case(select)
			1'b0: out=ain;
			//1'b1: out=bin;
		endcase
	end
endmodule