##tb.v (tb)
`timescale 1ns/100ps
module tb;
reg clk, rst;
wire [7:0] dout;
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial begin
rst = 1'b1;
#1 rst = 1'b0;
#2.5 rst = 1'b1;
// #340.9 rst = 1'b0; 验证复位信号作用
// #0.1 rst = 1'b1;
end
CNT10 U_CNT10
( .clk (clk ),
.rst (rst ),
.dout (dout ) );
endmodule
##test.do (sim)
# step 1
vlib work
# step 2
vlog ../rtl/cnt10.v
vlog ../tb/tb.v
#step 3
vsim tb
add wave -position insertpoint \
sim:/tb/clk \
sim:/tb/rst \
sim:/tb/dout
run 2us
##cnt10.v(rtl)
module CNT10 (clk, rst,dout );//二位十进制计数器0~99
input clk,rst;
output reg [7:0]dout;
reg q3;
reg [3:0] q1;//低位
reg [3:0] q2;//高位
always @ ( *