Power Distribution Network (PDN) and Chip Packaging

Sources and Resources:

[1] short description: Power Delivery Network (PDN) - Semiconductor Engineering

[2] PDN on PCB:

Power Distribution Network in PCB Design: Ensuring Stable Power Delivery

[3] lecture slides on "Packaging, Power, & Clock": https://pages.hmc.edu/harris/cmosvlsi/4e/lect/lect21.pdf

[4] (RLC) modelling of control system: 学子专区——二阶系统电子控制理论：为工程师提供的实用分析 | 亚德诺半导体

Power Distribution Network (PDN)[1]

Getting power around a semiconductor device is complicated and expensive. It generally starts at a power supply and [is] transferred by wires to a printed circuit board. Attached to that board are one or more ICs.

Traces on the PCB connect from the pads where the power supply wires are connected to the pad where power will be transferred to the chip. Those PCB traces may also involve vias that go through the PCB. To go from the chip pad into the chip will involve some kind [of] pin or bump and that has to be connected to the semiconductor surface – often involving a wire or other metal conductor and solder. Then a series of metal layer traces and vias, and potentially traces within the silicon, connect the transistors to the supply. Along that path, a set of resistances, capacitance and inductances are inherited that mean that what appears at the transistor is not a perfect replication of what came out of the power supply.

(Gemini) Q: read above and explain what are "trace", "pad", "pin", "bump" here, compare their roles and show some examples in actual pcb

A:

Trace: Imagine tiny copper wires etched onto the surface of the PCB. These are called traces.exclamation They act like miniature highways, carrying electrical signals (including power) between different components on the board.expand_more You can see them as thin, brown lines on a PCB .

source: PCB Trace: The Backbone of Modern Circuit Design

Pad: Pads are landing zones (exposed metal) for components like the IC They are typically round or oval-shaped metal areas on the PCB where traces connect. The pads provide a strong electrical connection point for soldering components onto the board.

source: What is a Pad in PCB Design and Development | Sierra Circuits

Pin: Pins are small metal legs that protrude from the body of an IC. These pins connect the internal circuitry of the chip to the external world through the PCB. During assembly, the pins are soldered onto the corresponding pads on the PCB.

(not quite on piont, but an image to showcase pin and socket)

Bump: Bumps are microscopic solder connections used in some advanced packaging technologies for ICs. Unlike pins, bumps are tiny solder balls directly on the chip's surface. They create a physical and electrical connection when the chip is placed on the PCB and heated to melt the solder.

image source: https://www.researchgate.net/figure/SEM-images-of-coined-solder-bumps-on-PCB-substrates-a-Top-view-b-cross-section-c_fig2_4025222

Component	Role	Example
Trace	Conducts electrical signals	Thin brown lines on the PCB
Pad	Provides connection point for components	Round or oval metal areas
Pin	Connects chip to PCB	Small metal legs on the IC
Bump	Microscopic solder connection for advanced packaging	Tiny solder balls on the chip's surface

Q: more on via

Via: Imagine a multi-story building. Regular traces act like hallways on each floor, but to move between floors, you need stairs or an elevator. Vias function similarly on a PCB. They are plated holes drilled through the PCB that connect traces on different layers. This allows for a more compact and efficient design by enabling signals and power to travel vertically through the board.

There are several types of vias, each suited for different situations:

• Through-hole via: The most common type. It goes through the entire thickness of the board, connecting all layers.

  ​​www.linkedin.com

  

• Blind via: Connects only some of the inner layers, not reaching the top or bottom surface of the PCB.

  ​camptechii.com

  

• Buried via: Completely buried within the inner layers of the PCB, not exposed on either surface.

  ​www.autodesk.com

  

Why use vias?

• Compactness: By connecting layers vertically, vias allow for denser circuitry on a smaller PCB footprint.
• Signal Integrity: Vias can help maintain signal integrity by providing shorter paths compared to routing traces on a single layer.
• Flexibility: They offer more routing options for complex designs.

Things to Consider with Vias:

• Via size: Smaller vias are generally preferred, but they can be limited by manufacturing capabilities and the desired electrical performance.
• Via placement: Careful placement is crucial to avoid signal integrity issues like crosstalk and impedance mismatch.
• Cost: More vias can increase fabrication cost.

Voltage regulators or converters may also be inserted anywhere along that path to provide the necessary voltages for various pieces of the circuit. In low power designs, switches may exist within the power supply to enable power to be removed from some parts of the circuit to reduce the leakage power. Because of peak current demands, capacitors may be added the retain enough charge to meet the instantaneous demand and are then recharged when less current is required.

Historically, the power delivery network (PDN) was overdesigned by adding significant margins to all aspects of the network, thus ensuring that timing or functional failures were not caused by an inadequate design. More recently, that level of margin can no longer be tolerated and so much more attention is being paid to the PDN and much more analysis is being performed on it. This is sometimes called power integrity analysis.

There are several aspects to this analysis. IR drop looks at the potential for the voltage on a transistor not being adequate and impacting timing and potential functional integrity. Electromigration looks at the likelihood that traces will age over time resulting in devices that prematurely fail. Noise analysis looks to see if sensitive circuitry will be affected either directly or through coupling.

Power Distribution Network in PCB Design: Ensuring Stable Power Delivery[2]

(this article is very long meant to actually cover many design tricks, while being not very concise; here only focus on fundamentals concepts and considerations)

A power distribution network (PDN) plays a vital role in PCB design; it ensures stable power delivery to all electronic components. It distributes power from the primary power source throughout the PCB board to ensure voltage supply to various components. PDN consists of traces, vias, planes, and decoupling capacitors; these are capacitors strategically laid out to minimize impedance and deliver clean and stable power to critical components.

Inadequate power distribution within a PCB board can have profound implications on circuit performance, reliability, and functionality. Without a robust PDN, electronic components may experience voltage droops, noise interference, and signal integrity issues, leading to erratic behavior and potential system failures.

Consequences of Poor PDN Design

Voltage Droops:
Inadequate power distribution can result in voltage drops. The voltage supplied to components can temporarily decrease during high-current demand, leading to malfunction or data corruption.

Noise Interference:
Poor PDN design can introduce noise into the power supply. This can cause fluctuations in voltage levels and disrupt the functionality of sensitive components. The noise can propagate through the circuit and can affect signal integrity and overall performance.

Signal Integrity Issues:
Unstable power delivery can manifest as signal integrity issues, such as ringing, overshooting, and undershooting. This compromises the accuracy and reliability of data transmission within the circuit.

Understanding the Basics: Power Distribution Network (PDN) in PCBs

Semiconductor devices require adequate power to function correctly. However, ensuring efficient power delivery poses a complex and costly challenge in electronics design.

It typically begins with a power supply transmitting power via wires to a PCB board. On this board, one or more integrated circuits (ICs) are affixed. Copper Traces on the PCB connect from the pads, where power supply wires are linked, to the pads that transfer power to the chip. These traces may utilize vias to traverse through the PCB board. Connecting from the chip pad to the chip involves pins or bumps that link to the semiconductor surface, often using wires or other conductive materials soldered in place. Subsequently, a network of metal layer traces, vias, and potential traces within the silicon connect the transistors to the power supply. However, this pathway inherits resistances, capacitances, and inductances, resulting in variations from the original power supply output at the transistor.

Overview of PDN Components and Their Functions

The PDN comprises several key components, each serving a specific function in ensuring efficient power distribution and noise suppression:

Power sources:
These are the leading suppliers of power to the PCB design board, consisting of batteries, power supplies, or external sources.

Traces:
Traces are conductive pathways that route power from the sources to individual components on the PCB design board. They play a crucial role in delivering power efficiently while minimizing impedance and voltage drops.

Planes: PCB board
planes are large copper areas on the board that act as low-impedance paths for power distribution. They provide a stable ground reference and help distribute power evenly across the board.

(Gemini)

Planes Explained:

Imagine a highway with multiple lanes for traffic flow. Planes on a PCB function similarly. They are large, uninterrupted areas of copper foil covering a significant portion of a PCB layer. These planes act as wide electrical conductors with very low electrical resistance (impedance). This allows for:

• Efficient Power Distribution: Power from the supply can travel through the plane with minimal signal loss, ensuring a steady voltage supply to various components on the board.
• Stable Ground Reference: One plane is typically designated as a ground plane. It provides a stable reference point (0 volts) for all the electrical signals on the PCB. This helps maintain signal integrity and reduces noise.

Types of Planes:

• Power Planes: These planes are dedicated to delivering power from the supply to different parts of the board. They can be connected to specific voltage rails depending on the power requirements of the components.
• Ground Planes: As mentioned earlier, these planes serve as the reference point for all ground connections on the PCB.

Points to Remember:

• Planes are not always solid copper sheets. Strategically placed slots or breaks can be incorporated for specific design needs.
• Plane connections to components and other traces are usually made through vias.

Decoupling Capacitors:
Decoupling capacitors are strategically placed throughout the PDN to absorb high-frequency noise and provide local energy storage. They help stabilize voltage levels and reduce voltage fluctuations caused by sudden changes in current demand.

Voltage Regulators: Voltage regulators control and regulate the voltage levels to ensure consistent power supply to sensitive components. They help maintain voltage stability, even in the presence of varying input voltages or load conditions.

Also Know: What Are the Challenges of Signal Integrity in High-Speed PCB Design?

Decoupling Capacitors in PDN Design: Strategies for Effective Bypassing

In the intricate landscape of PCB design, power integrity stands as a crucial aspect governing the reliability and performance of electronic systems. At the heart of power integrity lie two indispensable components: bypass capacitors and decoupling capacitors. While these capacitors are often conflated or their roles misunderstood, it’s imperative to discern their distinct functions and their impact on mitigating power integrity issues.

Two Related Power Integrity Problems

Decoupling capacitors and bypass capacitors are instrumental in addressing distinct yet interrelated power integrity challenges. Despite their terminology, which might imply diversion, these capacitors operate within the PDN to counteract voltage fluctuations and maintain signal integrity. The fundamental distinction lies in the fluctuations they mitigate and their placement within the circuit.

(from Wiki)

Role of Decoupling Capacitors in PDN Design

Decoupling capacitors helps reserve energy within the PDN. This enables instantaneous power to integrated circuits (ICs) while mitigating voltage fluctuations and noise. These capacitors act as a buffer, absorbing and releasing charge as needed to stabilize voltage levels and maintain signal integrity. Their placement near the power pins of ICs minimizes the inductance of the power delivery path, ensuring rapid response to transient currents and reducing voltage droops.

Strategies for Effective Bypassing

• Placing Capacitors Close to Power Pins:
  Proximity is critical in bypassing strategies. It reduces the inductance between capacitors and ICs and improves their effectiveness in filtering out noise. By placing decoupling capacitors closer to the power pins of ICs, a hardware designer minimizes the loop area and inductance. This can enhance noise suppression.
• Using a Combination of Capacitor Values:
  Employing capacitors with different values addresses a broader frequency range of noise. This enhances the PDN’s noise suppression capabilities across various frequencies. This also allows a hardware designer to target specific frequency ranges of noise and improve overall noise reduction.
• Implementing Multiple Layers of Decoupling Capacitors:
  A hardware design engineer can utilize capacitors with varying capacitance values on different layers of the PCB design board. This helps to optimize the PDN’s response to different frequency components of noise. Additionally, it allows for distributed capacitance, helping to reduce the overall impedance of the PDN and improve noise filtering performance.
• Employing Distributed Capacitance:
  Strategically placing capacitors throughout the PCB board creates a network of low-impedance paths. This reduces inductance and improves the PDN’s overall impedance profile. Moreover, it helps a hardware designer minimize voltage fluctuations and ensure stable power delivery to all components.
• Selection Criteria for Decoupling Capacitors:
  Capacitance value, voltage rating, and Equivalent Series Resistance (ESR) are critical factors to consider when choosing decoupling capacitors. High capacitance values and low ESR are desirable for effective noise filtering and voltage stabilization. Additionally, selecting capacitors with appropriate voltage ratings ensures reliability and longevity in operation.

Modeling PDN and IC System[4]

二阶系统

A second-order dynamic system is one whose response can be described by a second-order ordinary differential equation (ODE).

图1所示为最基础的二阶网络。

图1.由一个电阻、一个电感和一个电容构成的二阶网络。

其传递函数为：

some sentences in Chinese are very hard to read and I'll paste the English version:

The denominator of the right hand side of Equation 1 is known as the characteristic polynomial and if we equate the characteristic polynomial to zero, we get the characteristic equation. The poles of a system occur when the denominator of its transfer function equals zero. By finding the roots of the characteristic equation (the values of s that make the characteristic equation equal to zero), we can find the poles of the system and hence discover a wealth of information about how the system behaves.

Deriving the Transfer Function and Understanding Laplace Domain

(Gemini)

The transfer function of a circuit relates the input signal (voltage or current) to the output signal in the frequency domain. It's a powerful tool for analyzing the behavior of electrical networks. Here's how we get the transfer function and the concept of the Laplace domain:

Deriving the Transfer Function:

1. Writing Differential Equations: We start by writing the governing differential equations for the circuit. These equations relate the voltages and currents across the elements (R, L, and C) using Kirchhoff's Voltage Law (KVL) and Kirchhoff's Current Law (KCL) //recall: 

   Kirchhoff's current law (KCL) the algebraic sum of the currents flowing through a junction is zero.

   Kirchhoff's voltage law (KVL) The algebraic sum of the voltage difference in any loop must be zero.

2. Applying Laplace Transform: We then apply the Laplace transform to both sides of these differential equations. The Laplace transform converts a function of time (t) to a function of a complex variable (s). This transformation has some convenient properties:

   • Differentiation in the time domain becomes multiplication by s in the Laplace domain. (show case by comparing f(t) and f'(t) for some simple function in time domain, and also L(f) and L(f'))
   • Integration in the time domain becomes division by s in the Laplace domain.

   These properties simplify the differential equations significantly.

3. Solving for the Transfer Function: By manipulating the resulting algebraic equations (after applying Laplace transform), we can isolate the output variable (e.g., capacitor voltage) on one side and the input variable (e.g., input voltage) on the other side. This gives us the transfer function, which is the ratio of the Laplace transforms of the output and input signals (T(s) = Vout(s) / Vin(s)).

Example Transfer Functions for RLC

1. Series RLC Circuit:

In this configuration, the resistor, inductor, and capacitor are connected in series, with the input voltage applied across the entire series. The output can be taken across any element (resistor, inductor, or capacitor).

The transfer function (ratio of output voltage (Vout) to input voltage (Vin)) for this configuration depends on the chosen output point:

• Output across the resistor (Vout = VR):

T(s) = VR(s) / Vin(s) =  (1 / (L∙C)) / (s^2 + (R/L)s + (1/L∙C))

• Output across the inductor (Vout = VL):

T(s) = VL(s) / Vin(s) =  (s / (L∙C)) / (s^2 + (R/L)s + (1/L∙C))

• Output across the capacitor (Vout = VC):

T(s) = VC(s) / Vin(s) =  (1/C∙s) / (s^2 + (R/L)s + (1/L∙C))

2. Parallel RLC Circuit:

In this configuration, the resistor, inductor, and capacitor are connected in parallel, with the input voltage applied across all three elements in parallel. The output is typically taken across the capacitor.

The transfer function for this configuration (ratio of capacitor voltage (VC) to input voltage (Vin)) is:

T(s) = VC(s) / Vin(s) =  (1 / (s∙L + 1/C)) / (1 + (R∙C)s + (L∙C)s^2)

Workout the Transfer Function in Question:

Here's the KVL equation for the series RLC circuit:

Vin(t) - VR(t) - VL(t) - VC(t) = 0

where:

• Vin(t) is the input voltage as a function of time.
• VR(t), VL(t), and VC(t) are the voltage drops across the resistor, inductor, and capacitor, respectively, as functions of time.

We can express the voltage drops across each element using their relationships with current (i(t)) flowing through them:

• VR(t) = Ri(t) (Ohm's Law)
• VL(t) = L di(t)/dt (inductor voltage-current relationship)
• VC(t) = 1/C ∫ i(t) dt (capacitor voltage-current relationship)

Substituting these expressions into the KVL equation, we get:

Vin(t) - Ri(t) - L di(t)/dt - (1/C) ∫ i(t) dt = 0

3. Apply Laplace Transform:

Take the Laplace transform of both sides of the differential equation. Remember, the Laplace transform converts a function of time (t) to a function of the complex variable (s).

Applying the Laplace transform (denoted by L{}) and using the properties mentioned earlier (differentiation becomes multiplication by s, integration becomes division by s), we obtain:

Vin(s) - R I(s) - LsI(s) - (1/C) * (1/s) * I(s) = 0

where:

• Vin(s) is the Laplace transform of Vin(t)
• I(s) is the Laplace transform of i(t)

Vout = Vc = 1/(sC) * Is

(Vout*s/L) / (Vin*s/L) = (1/L/C)  / (s^2 + sR/L + 1/L/C). i.e. Eq. 1

Laplace Domain and the Variable "s":

The Laplace domain, denoted by "s," is a complex mathematical domain used to analyze systems described by linear differential equations. It essentially allows us to convert the analysis of a system from the time domain (where variables change with time) to the frequency domain (where variables are represented by their frequency components).

The complex variable "s" in the Laplace domain has two components:

* **Real part (σ):** Represents the exponential decay or growth of the signal. A positive real part indicates an exponentially decaying signal, while a negative real part indicates exponential growth (usually not desirable in circuits).
* **Imaginary part (ω):** Represents the frequency of the sinusoidal component of the signal. A purely imaginary value of "s" (ω ≠ 0) corresponds to a sinusoid with frequency ω.

By analyzing the transfer function in the s-domain, we can understand how the circuit responds to different input frequencies. This is crucial for tasks like designing filters, which manipulate specific frequency components of a signal.

Benefits of Transfer Functions:

• Provides a concise way to represent the relationship between input and output.
• Simplifies analysis by leveraging the properties of the Laplace transform.
• Offers insights into the frequency response of the circuit.

二阶系统传递函数的一般形式为：

其中ζ表示阻尼系数，ωn表示电路的固有振荡频率（或无阻尼频率），单位为弧度/秒。

所以，二阶系统的一般特性方程为：

比较方程3和方程1，我们可以看出，图1中的电路的固有频率为：

我们也可以看出，电路中的电阻会影响网络的阻尼系数：

所以

所以

可以直观看出，如果电路中没有电阻，网络不会出现耗损（无阻尼），如果模拟这种电路，则电路会永久振荡。随着电阻增加，振荡会更快衰减。

图2显示一个RLC电路，其中阶跃输入为1 V，L = 1 µH，C = 1 µF，电阻分别为0 Ω、100 mΩ和500 mΩ。电路按照预期的159 kHz频率振荡。电阻增加对衰减的影响一目了然。

图2.电阻对网络振荡的衰减影响。

我们可以通过将拉普拉斯域转换为时域，以数学方式展示图2所示的模拟结果。拉普拉斯域中的单位阶跃输入写为：

所以当我们使用单位阶跃输入仿真二阶系统时，结果会变成：

如果使用部份分式分解法，方程9可以写为：

方程10是表示在拉普拉斯域中的。

在时域中，这会转换为：

其中

采用逆拉普拉斯变换的公式11的数学推导如 附录A所示。

Equation 11 tells us how the circuit in Figure 1 responds to a step input. We can see that the waveform has a sinusoidal-like nature and its amplitude is modulated by the term e–ζωnt, which decays or grows exponentially depending on whether the damping coefficient is positive or negative. As an approximation, we can see that the response consists of a sinusoidal part and a cosinusoidal part, but, for low damping coefficients, the sinusoidal part is small.

Moreover, we can see that, although the natural frequency of the circuit is ωn, the circuit does not oscillate at this frequency but rather a frequency, ωd, that is somewhat lower and determined by the damping coefficient, ζ. This frequency is known as the damped natural frequency. Nevertheless, the exponential decay is dependent on the undamped natural frequency of the circuit, ωn.

要找出转换函数的极点，则需要确定转换函数何时等于0，也就是说：

s的值可以使用二次方程求解：

其中

a = 1

b = 2ζωn

c = ωn2

要得出系统极点，需要：

如果阻尼系数小于1，会得出负的平方根，所以最好将方程15写作：

我们之前说过 ωd = ωn√(1 – ζ2)，所以方程16可以改写为：

这里我们可以看出，系统的极点包含实数部分(–ζωn)和虚数部分(±jωd)。

方程17可以求解得出特性方程的根（系统的极点）。我们如何将这些极点与系统的稳定性联系起来？现在我们需要把拉普拉斯域的极点和时域的稳定性联系起来。

通过方程11和方程17，我们可以得出以下观察结果。

无阻尼固有频率ωn决定了：

• 拉普拉斯域（方程17）中的极点(–ζωn)的虚数部分。
• 振荡的实际频率

由此，可以合理假设极点的虚数部分确定了系统振荡的实际频率。

这两个假设可以用s平面图表示，我将在下一节详细介绍。

稳定的系统

控制理论认为，如果极点位于s平面的左半部分，则系统是稳定的。图3所示为一个s平面示例，其中实数部分在x轴上绘制，虚数部分在y轴上绘制。

图3.s平面：显示稳定的左半部分和不稳定的右半部分。

从方程17可以看出，如果阻尼系数为正（方程17的实数部分为负），则极点位于左半部分。随着阻尼系数增加，方程17的极点进一步向左移动（在左侧平面内，越来越靠近左侧)。

如果方程17在拉普拉斯域中，如何在时域中转换？

为了方便起见，我们再次使用方程11：

正阻尼系数ζ会引发指数式的衰减幅度响应（由e–ζωnt项表示），阻尼越大，衰减越快。随着阻尼系数增加，极点进一步向左移动（在拉普拉斯域内），这进一步增大了时域内的指数式衰减。从图2中可以看出这一点，图2使用100 mΩ和500 mΩ线路来表述电阻对阻尼的影响。在此区域中，500 mΩ线路的阻尼系数最大，所以它的指数式衰减最明显。0 Ω时，阻尼系数为0，此时极点完全位于y轴上，电路无限振荡，如图2中的绿色线路所示。

值得注意的是，即使系统是稳定的，这并不表示一定没有振荡。电路可能会在左半平面的极点处振荡，但是这些振荡的振幅会随着时间而衰减，如图2所示。

这对图1中的电路意味着什么?

我们知道图1中的阻尼是通过下方的方程得出：

它的固有频率则是：

所以，在L = 1 µH，C = 1 µF时，固有频率为1 Mrads–1 (= 159.1 kHz)，R = 500 mΩ时的阻尼系数为0.25。

所以，阻尼振荡频率ωd由以下方程计算得出：

所以，阻尼振荡频率为968 krads–1，即154 kHz。这可以通过查看图4中红色波形的频率来说明。

图4.阻尼对RLC电路振幅和频率的影响。

正弦波的振幅按e–ζωnt衰减。阻尼系数为0.25，固有频率ωn为1 Mrads–1，阻尼固有频率为968246 rads–1，那么方程11变成：

使用这个公式，计算得出VOUT在3.26 μs时为1.44 V，在9.75 μs时为1.09 V，与图4中显示的读数完全一致。

图4清楚显示了增加阻尼系数会产生的影响，即振幅和阻尼固有频率都减小。

如果我们继续增大阻尼系数，会出现什么结果？

我们知道阻尼固有频率是通过以下方程计算得出：

当阻尼系数增大到一时，阻尼固有频率减小到零。这就是所谓的临界阻尼点，此时电路中的所有振荡终止。这一点可参见方程11。自阻尼固有频率ωd减小到0，正弦项等于0，余弦项目等于一，表达式简化为一阶系统，与通过电阻充电的电容完全一样。

这一点可以参见图4中的临界阻尼线路。

不稳定系统

由于所有电路都具有电阻，所以许多电子控制电路的极点都位于左半平面，且系统本身保持稳定。但是，由方程11可以看出，负阻尼系数会导致振幅响应呈指数增长，所以极点位于右半平面会导致系统不稳定。在电路模拟中，通过插入负电阻，可以很容易看出右半平面的影响。图5显示RLC电路，其电阻为负。

==>Negative Resistance is described by a component that decreases the circuit current with increasing voltage; a rea life example is a fluorescent lights.

图5.电阻为负的RLC电路。

该电路的阻尼系数为-0.1。图6显示了它对阶跃输入的响应。

图6.阻尼为负的二阶系统的阶跃响应。

阻尼固有频率仍然由以下方程表示：

阻尼系数为-0.1时，振荡的实际频率为994987 rads–1 (158.3 kHz)。

同样，从方程11可以看出电路响应由以下公式表示：

在输出增大时，我们可以得出振幅响应：VOUT在41.05 μs时，计算得出的值为61.62 V，在47.36 μs时，为114.99 V，与图6中所示的读数完全一致。

主导极点

有时一个系统由许多极点组成，使分析变得复杂。但是，如果极点之间相隔的距离足够大，那么一个极点产生的影响会占主导，因此可以忽略非主导极点，从而简化系统。

图7的上半部分显示了两个RLC电路，每个都使用完全相同的L和C元件；只是电阻发生了变化。电阻较低的电路的极点更靠近s平面的虚数轴。

图7.主导极点的位置对串联和并联电路的影响。

图7的下半部分显示了这两个电路的串联。我们使用行为电压源B1来复制V(OUT3)，以免它被R4、L4和C4加载，以便我们查看V(OUT3) × V(OUT4)的真实响应。

图8.当两个波形相加或相乘时，主导极点对系统响应的影响。

我们可以参考图8查看它们的响应。不出所料，电阻最大的电路具有最大的阻尼系数，因此其振荡衰减也最快，如图V(OUT2)所示。但是，我们注意到，当两个输出要么相加（使电路并联），要么相乘（使电路串联）时，V(OUT1)在响应中占主导。因此，要简化复杂的系统，方法之一是重点关注极点更靠近jω轴的电路，该电路会主导整个系统的响应。

在左右半面均有极点分布的系统

我们已经考虑过极点位于左半平面或右半平面的系统。如果系统在左右半面均有极点分布，会怎么样？哪一种在稳定性方面更胜一筹？为什么？

我们再次参考方程11，可以看出指数是决定系统是否稳定的决定因素。我们可以忽略方程11的正弦部分，只看指数，以了解如果我们将左半面的极点和右半面的极点结合，会发生什么。图9通过一个简单电路来进行演示。

图9.极点分别位于左半面和右半面的电路。

很显然，顶部的RC电路的极点位于左半面，因为它的电阻为正。底部电路的极点则位于右半面。得出此结论的数学推导如附录B所示。

图9中，电路的响应如图10所示。

图10.对具有正负电阻的RC电路的阶跃输入的响应。

顶部波形在大约5毫秒后稳定在零梯度，这符合大众接受的规则，即RC电路将稳定在大约5个时间常数。相反，V(OUT2)的梯度不断增加。现在可以明显看出，如果将极点位于左半面的电路和极点位于右半面的电路串联，那么整个电路会不稳定，这是因为在左半面电路稳定很长时间后，右半面电路的响应会继续呈指数上升。因此，为了让电路稳定，所有极点都必须位于左半面。

结论

本文将电子控制理论中使用的理论模型与电子工程师所处的现实联系起来。受系统中的电阻（或阻尼）影响，只有当所有极点都位于左半面时，控制系统才会保持稳定。对于极点位于右半面的系统，通过测量其输出响应，结果证实存在问题，因为这需要构建负电阻模型。幸好，计算机模拟帮我们解决了这个问题，让我们能够通过简单变更电阻的极性来展示稳定和不稳定的电路。

同样，拉普拉斯变换也很少在课堂之外出现，但在验证二阶电子系统如何工作时，它们的作用可谓是无价的。

附录

下载与本文相关的 LTspice® files 文件。

欲了解有关LTspice的更多信息，请访问analog.com/ltspice。

参考电路

Charles Phillips、Royce Harbor。《反馈控制系统》，第4版。Prentice Hall International，1988年。

How PDN and Packaging Affect Chip Design

Besides the obvious PI design standards (MaxPower, Vmin, TDP) that must be met by PDN for correct chip behavior, PDN design together with chip packaging would have a compounding influence when coupled with frequently changing chip current behaviors.

PDN usually provide grouped and level delivery to chips in a system (say one PCB), and the noise frequency for power delievered to a given chip is usually governed by the RLC modelling of the PDN.

The end goal for any PDN is to main stable Vdd, given P = VI, and V, I are dictated by the switching behavior of the chip, when the RLC noise of a PDN (or its subsystem) is in resonance with current behavior frequency, with a phase shift that match trough of Power to peak of current, then we would have the minimum possible Vdd for the chip, if said Vmin cannot satisfy chip design minimum, then we would have undefined behaviors.  

To visualize the system abstraction, see [3]:

a packaged chip:

a PDN-IC system:

In general we can use the the PDN's perspective and regard the IC-package as a blackbox, providing an arbitrary stimulus to PDN by its switch behavior, which is in turn purely determined by computation workload for IC.

The PDN will transition from its base stable state to the activated stable state, and it will oscillate, introducing voltage noise according to its RLC property.