验证ZC706Pro的10G光口

最新推荐文章于 2024-06-17 12:55:48 发布

mcupro

最新推荐文章于 2024-06-17 12:55:48 发布

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分类专栏：软件无线电 SDRPI 文章标签：网络 linux 运维

本文链接：https://blog.csdn.net/mcupro/article/details/127210927

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首先我基于之前的一个7K325的光口设计进行修改，主要修改两点:XDC引脚锁定文件和选择芯片型号为7Z045-FFG900。

1,首先找到以前的硬件并且搭建起来运行环境。

2,可以看到UDP ECHO成功。两个端口都进行了实验都OK.

3,修改XDC文件对应原理图。

原来的XDC文件：


set_property PACKAGE_PIN F6 [get_ports ref_clk_p0]

create_clock -period 6.400 -name ethclk0 -waveform {0.000 3.200} [get_ports ref_clk_p0]

set_property PACKAGE_PIN G12 [get_ports tx_disable0]
set_property IOSTANDARD LVCMOS25 [get_ports tx_disable0]

set_property PACKAGE_PIN J13 [get_ports tx_disable1]
set_property IOSTANDARD LVCMOS25 [get_ports tx_disable1]

set_property PACKAGE_PIN A4 [get_ports mgt_tx_p0]
set_property PACKAGE_PIN B2 [get_ports mgt_tx_p1]


set_property PACKAGE_PIN A15 [get_ports led_up]
set_property IOSTANDARD LVCMOS25 [get_ports led_up]
set_property PACKAGE_PIN B12 [get_ports led_dwn]
set_property IOSTANDARD LVCMOS25 [get_ports led_dwn]


 
set_property CONFIG_VOLTAGE 2.5 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design]
set_property BITSTREAM.CONFIG.TIMER_CFG 2000000 [current_design]
set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]


set_false_path -from [get_pins {tengbaser_infra0_inst/ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_shared_clock_reset_block/reset_pulse_reg[0]_replica/C}] -to [get_pins {tengbaser_infra0_inst/ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_shared_clock_reset_block/gttxreset_txusrclk2_sync_i/sync1_r_reg[*]/PRE}]

对照原理图修改后的XDC文件：


#bank 112
set_property PACKAGE_PIN r8 [get_ports ref_clk_p0]

create_clock -period 6.400 -name ethclk0 -waveform {0.000 3.200} [get_ports ref_clk_p0]

set_property PACKAGE_PIN aa18 [get_ports tx_disable0]
set_property IOSTANDARD LVCMOS25 [get_ports tx_disable0]

set_property PACKAGE_PIN ad20 [get_ports tx_disable1]
set_property IOSTANDARD LVCMOS25 [get_ports tx_disable1]

#bank 111
set_property PACKAGE_PIN w4 [get_ports mgt_tx_p0]
set_property PACKAGE_PIN v2 [get_ports mgt_tx_p1]


#set_property PACKAGE_PIN A15 [get_ports led_up]
#set_property IOSTANDARD LVCMOS25 [get_ports led_up]
#set_property PACKAGE_PIN B12 [get_ports led_dwn]
#set_property IOSTANDARD LVCMOS25 [get_ports led_dwn]


 
#set_property CONFIG_VOLTAGE 2.5 [current_design]
#set_property CFGBVS VCCO [current_design]
#set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
#set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
#set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design]
#set_property BITSTREAM.CONFIG.TIMER_CFG 2000000 [current_design]
#set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]


set_false_path -from [get_pins {tengbaser_infra0_inst/ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_shared_clock_reset_block/reset_pulse_reg[0]_replica/C}] -to [get_pins {tengbaser_infra0_inst/ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_shared_clock_reset_block/gttxreset_txusrclk2_sync_i/sync1_r_reg[*]/PRE}]