SY AD15 FPGA1约束文件

最新推荐文章于 2024-07-16 15:18:58 发布
钟山翼
最新推荐文章于 2024-07-16 15:18:58 发布
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分类专栏： module
本文链接：https://blog.csdn.net/lengtian90/article/details/110673004
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set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE Yes [current_design]

#############################################衍生时钟约束
create_generated_clock -name GK3128_1_SLCLKAB_108m -source [get_pins GK3128_inst1/clk_wiz_AB/inst/mmcm_adv_inst/CLKIN1] [get_pins GK3128_inst1/clk_wiz_AB/inst/mmcm_adv_inst/CLKOUT0] 
create_generated_clock -name GK3128_1_SLCLKCD_108m -source [get_pins GK3128_inst1/clk_wiz_CD/inst/mmcm_adv_inst/CLKIN1] [get_pins GK3128_inst1/clk_wiz_CD/inst/mmcm_adv_inst/CLKOUT0] 
#############################################伪时钟路径约束
set_false_path -from [get_clocks GK3128_1_CLKAB_P] -to [get_clocks GK3128_1_SLCLKAB_108m]
set_false_path -from [get_clocks GK3128_1_CLKCD_P] -to [get_clocks GK3128_1_SLCLKCD_108m]
#############################################灯的物理约束
set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}]
set_property PACKAGE_PIN U24 [get_ports {LED[0]}]
set_property PACKAGE_PIN V24 [get_ports {LED[1]}]
set_property PACKAGE_PIN W21 [get_ports {LED[2]}]
set_property PACKAGE_PIN W22 [get_ports {LED[3]}]
#############################################板载时钟的物理约束
set_property IOSTANDARD LVCMOS33 [get_ports SYS_CLK]
set_property PACKAGE_PIN T26 [get_ports SYS_CLK]

set_property IOSTANDARD LVDS [get_ports FPGA_CLK_P]
set_property PACKAGE_PIN AD12 [get_ports FPGA_CLK_P]

####################AD2  GK3128###################################
set_property PACKAGE_PIN L25 [get_ports GK3128_1_CLKAB_P]
set_property PACKAGE_PIN C25 [get_ports GK3128_1_CLKCD_P]
set_property IOSTANDARD LVDS_25 [get_ports GK3128_1_CLKAB_P]
set_property IOSTANDARD LVDS_25 [get_ports GK3128_1_CLKCD_P]

set_property PACKAGE_PIN L30 [get_ports {GK3128_1_DAB_P[13]}]
set_property PACKAGE_PIN M29 [get_ports {GK3128_1_DAB_P[12]}]
set_property PACKAGE_PIN L22 [get_ports {GK3128_1_DAB_P[11]}]
set_property PACKAGE_PIN N29 [get_ports {GK3128_1_DAB_P[10]}]
set_property PACKAGE_PIN M20 [get_ports {GK3128_1_DAB_P[9]}]
set_property PACKAGE_PIN L26 [get_ports {GK3128_1_DAB_P[8]}]
set_property PACKAGE_PIN M28 [get_ports {GK3128_1_DAB_P[7]}]
set_property PACKAGE_PIN J27 [get_ports {GK3128_1_DAB_P[6]}]
set_property PACKAGE_PIN K26 [get_ports {GK3128_1_DAB_P[5]}]
set_property PACKAGE_PIN M24 [get_ports {GK3128_1_DAB_P[4]}]
set_property PACKAGE_PIN J23 [get_ports {GK3128_1_DAB_P[3]}]
set_property PACKAGE_PIN J21 [get_ports {GK3128_1_DAB_P[2]}]
set_property PACKAGE_PIN L21 [get_ports {GK3128_1_DAB_P[1]}]
set_property PACKAGE_PIN J29 [get_ports {GK3128_1_DAB_P[0]}]
set_property PACKAGE_PIN D26 [get_ports {GK3128_1_DCD_P[13]}]
set_property PACKAGE_PIN C24 [get_ports {GK3128_1_DCD_P[12]}]
set_property PACKAGE_PIN E23 [get_ports {GK3128_1_DCD_P[11]}]
set_property PACKAGE_PIN B23 [get_ports {GK3128_1_DCD_P[10]}]
set_property PACKAGE_PIN F25 [get_ports {GK3128_1_DCD_P[9]}]
set_property PACKAGE_PIN E24 [get_ports {GK3128_1_DCD_P[8]}]
set_property PACKAGE_PIN A25 [get_ports {GK3128_1_DCD_P[7]}]
set_property PACKAGE_PIN B28 [get_ports {GK3128_1_DCD_P[6]}]
set_property PACKAGE_PIN C29 [get_ports {GK3128_1_DCD_P[5]}]
set_property PACKAGE_PIN D29 [get_ports {GK3128_1_DCD_P[4]}]
set_property PACKAGE_PIN E28 [get_ports {GK3128_1_DCD_P[3]}]
set_property PACKAGE_PIN G23 [get_ports {GK3128_1_DCD_P[2]}]
set_property PACKAGE_PIN G28 [get_ports {GK3128_1_DCD_P[1]}]
set_property PACKAGE_PIN B27 [get_ports {GK3128_1_DCD_P[0]}]

set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DAB_P[13]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DAB_P[12]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DAB_P[11]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DAB_P[10]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DAB_P[9]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DAB_P[8]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DAB_P[7]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DAB_P[6]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DAB_P[5]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DAB_P[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DAB_P[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DAB_P[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DAB_P[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DAB_P[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DCD_P[13]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DCD_P[12]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DCD_P[11]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DCD_P[10]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DCD_P[9]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DCD_P[8]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DCD_P[7]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DCD_P[6]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DCD_P[5]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DCD_P[4]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DCD_P[3]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DCD_P[2]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DCD_P[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {GK3128_1_DCD_P[0]}]

set_property PACKAGE_PIN AJ2 [get_ports GK3128_1_SCLK]
set_property PACKAGE_PIN AJ1 [get_ports GK3128_1_SDATA]
set_property PACKAGE_PIN AK1 [get_ports GK3128_1_SEN]
#set_property PACKAGE_PIN AH2 [get_ports GK3128_1_RESET]
#set_property PACKAGE_PIN AJ3 [get_ports GK3128_1_SDOUT]


set_property IOSTANDARD LVCMOS18 [get_ports GK3128_1_SDATA]
set_property IOSTANDARD LVCMOS18 [get_ports GK3128_1_SCLK]
set_property IOSTANDARD LVCMOS18 [get_ports GK3128_1_SEN]
#set_property IOSTANDARD LVCMOS18 [get_ports GK3128_1_RESET]
#set_property IOSTANDARD LVCMOS18 [get_ports GK3128_1_SDOUT]

set delay_min 1.730;
set delay_max 5.330;

set_input_delay -clock [get_clocks GK3128_1_CLKAB_P] -clock_fall -min -add_delay $delay_min [get_ports {GK3128_1_DAB_P[*]}]
set_input_delay -clock [get_clocks GK3128_1_CLKAB_P] -clock_fall -max -add_delay $delay_max [get_ports {GK3128_1_DAB_P[*]}]
set_input_delay -clock [get_clocks GK3128_1_CLKAB_P] -min -add_delay $delay_min [get_ports {GK3128_1_DAB_P[*]}]
set_input_delay -clock [get_clocks GK3128_1_CLKAB_P] -max -add_delay $delay_max [get_ports {GK3128_1_DAB_P[*]}]
set_input_delay -clock [get_clocks GK3128_1_CLKCD_P] -clock_fall -min -add_delay $delay_min [get_ports {GK3128_1_DCD_P[*]}]
set_input_delay -clock [get_clocks GK3128_1_CLKCD_P] -clock_fall -max -add_delay $delay_max [get_ports {GK3128_1_DCD_P[*]}]
set_input_delay -clock [get_clocks GK3128_1_CLKCD_P] -min -add_delay $delay_min [get_ports {GK3128_1_DCD_P[*]}]
set_input_delay -clock [get_clocks GK3128_1_CLKCD_P] -max -add_delay $delay_max [get_ports {GK3128_1_DCD_P[*]}]

set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk_50m]