只有一个元素的异步FIFO

module one_entry_fifo #(parameter dw=16 )(

        input	rd_clk, wr_clk, rd_rst_n,wr_rst_n,we,re,

        input	[dw-1:0]	d ,reset_value,

        output	reg [dw-1:0]	q ,

        output	 reg  empty , full 

    );

    //synopsys sync_set_reset "rd_rst_n,wr_rst_n"

wire legal_wr  =  we  &(~full);

wire legal_rd  =  re & (~empty) ;

reg wr_ptr ,rd_ptr ;// only one bit !

reg wr_ptr_r,wr_ptr_rr; 

reg rd_ptr_r,rd_ptr_rr; 







always @(posedge rd_clk)wr_ptr_r <=wr_ptr;

always @(posedge rd_clk)wr_ptr_rr <=wr_ptr_r; 




always @(posedge wr_clk)rd_ptr_r <= rd_ptr;

always @(posedge wr_clk)rd_ptr_rr <= rd_ptr_r; 




always @(posedge rd_clk)if( wr_ptr_rr == rd_ptr ) empty<=1;else empty <= legal_rd ; 

always @(posedge wr_clk)if( rd_ptr_rr != wr_ptr ) full<=1 ;else full <= legal_wr ; 




always @(posedge rd_clk)if (~rd_rst_n)  rd_ptr <= 0;else  if ( legal_rd ) rd_ptr <= ~ rd_ptr ;

always @(posedge wr_clk)if (~wr_rst_n)  wr_ptr <= 0;else  if ( legal_wr ) wr_ptr <= ~ wr_ptr ;




reg [dw-1:0] buff ;  always @(posedge wr_clk)if ( legal_wr ) buff <= d ;

always @(posedge rd_clk)if ( ~rd_rst_n ) q <= reset_value ;else if ( legal_rd ) q <= buff; 







endmodule

 

因为只有一个元素，所以避免了使用格雷码来传递计数器。
应用场合：
1 ，跨时钟区域的信号，数据传递。
2，结合单时钟FIFO组成更大的容量的异步FIFO(和同步FIFO连接时候注意空和满标志的处理)。