1.cache line
valid/tag/block 构成cache line, ARM v8 cache line为例
Valid :有效位的标识符?
Tag:指示内存地址
Block: cache line存储cache
line中的数据,每个cache line可能有很多个block
D:dirty位
Arm v8中关于Cache
line:
Each line in the cache includes:
• A tag value from the associated Physical Address.----tag
• Valid bits to indicate whether the line
exists in the cache, that is whether the tag is valid.—valid
Valid bits can also be state bits for MESI
state if the cache is coherent across multiple
cores.-----MESI(cahe一致性相关状态)
• Dirty data bits to indicate----dirty位
2.cache组成结构有三种
Direct mapped 直接映射-----每个set只有一个cache line
Set associative 组关联----每个set有多个cache line
Full associative 全关联 ----只有一个set
关于cache地址映射的比较通俗的解释