USB4规范解读(六):USB4系统结构的架构之主要特性

本文详细解读USB4系统结构,重点介绍了其七大主要特性,包括高吞吐量信令速率、逐跳流量控制、带宽管理与优先级、编程模型、时间同步协议、错误检测与恢复以及链路级电源管理。USB4规范整合了雷电3协议,支持USB Type-C接口,确保高速数据传输和多协议兼容。
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USB4规范就是在USB 3.2规范的基础上,引入了雷电3协议规范。而雷电3协议就是DP(全名称为DisplayPort)视频协议和PCIe数据协议的结合。USB4系统结构组成为USB4主机和USB4设备,而USB4设备有USB4集线器和USB4外部设备两种。USB4系统结构支持传输高速的数据,那么需要满足哪些要求呢?本文就来讲解USB4系统结构的架构的主要特性。

USB4概念图

 

上图为USB4概念图,不是实际的USB4产品。USB4数据只支持USB Type-C接口,在USB4系统结构中传输。USB4系统结构旨在满足多种协议传输的需求,总共可以抽象出7种主要特性,下面逐一介绍这7种主要特性。

USB4系统结构的特性

一、支持高吞吐量互连的信令速率

  • 10 Gbps(适用于第二代,即USB4 Gen 2)和20 Gbps(适用于第三代,即USB4 Gen 3)。

  • 可选支持10.3125 Gbps的雷电3兼容速率(适用于第二代,即USB4 Gen 2)和20.625 Gbps(适用于第3代,即USB4 Gen 3)。40Gbps的速率是USB4 Gen 3x2,即两个通道传输。

1.1、吞吐量

互连的USB4端口单位时间内成功传输数据的数量。高吞吐量指的是传输数据量很大。

1.2、信令

信号传输时,其中一部分是需要传输的数据,另外一部分是用来专门控制电路的,用于控制的信号就是信令。此处的“信令”一词指的是信令控制传输数据的过程。

 

二、逐跳,基于信用的流量控制。

2.1、逐跳

逐跳,指的是一跳一跳(Hop-by-H

This chapter presents an overview of Universal Serial Bus 4 (USB4™) architecture and key concepts. USB4 is similar to earlier versions of USB in that it is a cable bus supporting data exchange between a host computer and a wide range of simultaneously accessible peripherals. However, USB4 also allows a host computer to setup data exchange between compatible peripherals. The attached peripherals share bandwidth as configured by the host computer. The bus allows peripherals to be attached, configured, used, and detached while the host and other peripherals are in operation. When configured over a USB Type-C® connector interface, USB4 functionally replaces USB 3.2 while retaining USB 2.0 bus operating in parallel. Enhanced SuperSpeed USB, as defined in USB 3.2, remains the fundamental architecture for USB data transfer on a USB4 Fabric. The difference with USB4 versus USB 3.2 is that USB4 is a connection -oriented, tunneling architecture designed to combine multiple protocols onto a single physical interface, so that the total speed and performance of the USB4 Fabric can be dynamically shared. USB4 allows for USB data transfers to operate in parallel with other independent protocols specific to display, load/store and host-to-host interfaces. Additionally, USB4 extends performance beyond the 20 Gbps (Gen 2 x 2) of USB 3.2 to 40 Gbps (Gen 3 x 2) over the same dual-lane, dual-simplex architecture. This specification introduces the concept of protocol tunneling to USB bus architecture. Besides tunneling Enhanced SuperSpeed USB (USB3), display tunneling based on DisplayPort (DP) protocol and load/store tunneling based on PCI Express (PCIe) are defined. These protocol tunnels operate independently over the USB4 transport and physical layers. Additionally, USB4 allocates packets for bus configuration and management, and packe ts can be allocated specifically for host-to-host data connections.
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