Tomasulo’s Approach

When we issue instructions in-order but execute them out-of-order, RAW, WAR and WAW hazard will emerge. By forcing every instruction to await its operands and track the instructions which  produce those operands, RAW is eliminated. WAR and WAW are attacked by register renaming.

How to accomplish it is depicted in page191 of CAAQA, and the item that must be noticed is all instructions are issued in-order but executed out-of-order.

1.Eliminating WAW hazard:

DIV        F1,F2,F3           ;F2/F3->F1

ADD       F1,F4,F5          ;F4+F5->F1

We know DIV operation takes longer time than ADD’s, and ADD surely will finish before DIV here. Does F1 have the correct value ultimately? We say yes, because these two instructions are issued in-order, and register F1 will first track the result of DIV, and when ADD is issued, F1 will turn to track the result of ADD, so when ADD finishes, it’s result will be stored to F1 with CDB, but when DIV subsequently finishes, it will never influence the value of register F1, because the result can only be stored into a place which is tracking this result. So WAW hazard is eliminated.

2.Eliminating WAR hazard is much easier, unnecessary to post nonsense here.