前言
继续思考如何让代码变得漂亮!
思前想后,我决心从一行的assign语句入手,毕竟这是我现在写的最多的语句了,主体漂亮那么整体也不会太差!
核心代码
大体的思路就是,从RTL中把assign = xxxxx;这类一行assign抓出来,然后把逻辑由空格打碎,当
1.一段逻辑超过了一定长度(暂定40)且符号完备(左括号和右括号一样多,(){}这两种),那么就可以换行;
2.一段路基超过了很长的长度(暂定80),那就强制换行;
def meihua_assign():
global assign_tab
global expr_tab
for line in file_hand:
result = re.match(r"(\s*)(assign)\s+(\w+)\s*=\s*([^/]+)(\/\/.*)?", line)
if result:
if result.group(1):
assign_tab = 4
sig_name = result.group(3).strip()
expr_cal = result.group(4).strip()
if re.match(r".*;", expr_cal):
if len(expr_cal) > 60: # need huanhang
expr_cal_list = expr_cal.split(" ")
out_logic = ""
out_num = 0
out_tail = ""
for sub in expr_cal_list:
sub = sub.strip()
sub = re.sub(r"\s*", "", sub)
match = 0
out_logic = out_logic + " " + sub
if cpt_logic(out_logic) == 1 and len(out_logic) > 40 and re.search(r"[^\w\(\)]", sub):
match = 1
if len(out_logic) > 80:
match = 1
if match == 1:
if out_num == 0:
str = "assign " + "%*s" % (Signal.name_width, sig_name) + " = " + out_logic.strip()
out_num = out_num + 1
else:
str = "%*s" % (expr_tab, " ") + out_logic.strip()
print(str)
out_logic = ""
out_tail = out_logic
if len(out_tail) > 0:
str = "%*s" % (expr_tab, " ") + out_tail.strip()
print(str)
else:
expr_cal = re.sub(r"\s+", " ", expr_cal)
str = "assign " + "%*s" % (Signal.name_width, sig_name) + " = " + expr_cal
print(str)
效果展示
开始我有这样一段代码:
assign data_out_ff1 = fb_cnt + data_out_vld_ff1 | (eop_out_vld_ff1 + ((&sop_out_vld_ff1) * (fb_eop + eop_out_vld_ff1))) + (sop_out_vld || (sop_out_vld_ff1 + data_out_ff1));
assign data_out_ff2 = data_out_vld_ff1 ? (sop_out_vld_ff1 & fb_cnt) + data_out_vld_ff1 | (eop_out_vld_ff1 + ((&sop_out_vld_ff1) * (fb_eop + eop_out_vld_ff1))) + (sop_out_vld || (sop_out_vld_ff1 + data_out_ff1)) : fb_cnt + data_out_vld_ff1 | (eop_out_vld_ff1 + ((&sop_out_vld_ff1) * (fb_eop + eop_out_vld_ff1))) + (sop_out_vld || (sop_out_vld_ff1 + data_out_ff1));;
assign fb_cnt = (sop_in_vld << 12) + 12'd52;
assign data_in_vld = (fb_cnt >> 2 + data_out_vld_ff1) || fb_cnt - (10'hd - eop_out_vld_ff1) && fb_vld + sop_in_vld * (data_out_ff1 + sop_out_vld_ff1) ;
assign data_in = fb_cnt + data_out_vld_ff1 | eop_out_vld_ff1;
assign data_in = fb_cnt + data_out_vld_ff1 | eop_out_vld_ff1;
assign data_in = fb_cnt + data_out_vld_ff1 | eop_out_vld_ff1 + data_out_vld_ff1 + data_out_vld_ff1 + data_out_vld_ff1 + data_out_vld_ff1;
函数处理一下之后:
怎么说呢,我觉还行哈哈哈哈哈