//module shift(clk,out,in,res,en,x_out);
// input clk;//时钟信号端口
// input res;//高电平复位信号端口
// input en;
// input [7:0]in;//8个比特位输入信号端口
// output reg[7:0]out;//8个比特位输出信号端口
// output wire[7:0]x_out;//循环移位输出信号端口
//
assign out = in;
// reg [7:0]x_temp;//用于循环移位赋值
//
// always @(posedge clk)begin
// if(res)begin//高电平复位
// out<=8'b0;
// end
// //移位和赋值
// else if(en) begin
out<=in;//单一赋值
//
// //右移位是把低位拿走。
out<={in[0],in[7:1]};//右移一位
//
// //左移位是把高位拿走。
// out<={in[6:0],in[7]};//左移一位
// x_temp<=in;
// end
// //循环移位
// else begin
x_temp<={x_temp[0],x_temp[7:1]};//右循环移位
// x_temp<={x_temp[6:0],x_temp[7]};//左循环移位
// end
// end
//
// assign x_out=x_temp;
//endmodule
//00000000000000000000000000000000000000000000000000000000000000
//串口,并口之间转换
//00000000000000000000000000000000000000000000000000000000000000
module Serial_parallel(clk,re,in,in_s,o_q,sp_en,o_p_q);
input clk;//时钟信号端口
input in;//串口输入信号端口
input [7:0]in_s;//并口输入信号端口
input sp_en;//高电平串口转并口,低电平并口转串口
input re;//高电平复位信号端口
output reg[7:0]o_q;//并口输出信号端口
output reg o_p_q;//串口输出信号端口
reg [7:0]x_temp;
integer i;
always @(posedge clk)begin
if(re)begin//高电平复位
o_q<=8'b0;
end
//否侧不是高电平,低电平判断sp_en是高电平串行转换并行
//sp_en低电平并行转换串行
else if(sp_en) begin
// o_q<={o_q[6:0],in};
o_q<={in,o_q[7:1]};
x_temp=in_s;//把输入并行输入赋值给临时寄存器
end
else begin
o_p_q<=x_temp[0];
x_temp<={x_temp[6:0],x_temp[7]};左循环移位
end
end
endmodule
//00000000000000000000000000000000000000000000000000000000000000
//仿真验证
//00000000000000000000000000000000000000000000000000000000000000
`timescale 1 ps/ 1 ps
module shift_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk=0;
reg res;
reg en;
reg [7:0] in;
// wires
wire [7:0] out;
wire [7:0] x_out;
// assign statements (if any)
shift i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.in(in),
.res(res),
.out(out),
.en(en),
.x_out(x_out)
);
parameter s_clk=40000;
always #s_clk clk=~clk;
initial
begin
// code that executes only once
// insert code here --> begin
res=1'b1;//初始化复位信号高电平
#(s_clk*2) res=1'b0;
en=1'b1;
#(s_clk*2) en=1'b0;
// --> end
$display("Running testbench");
end
always
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin
#(s_clk*2) in=8'b0100_0010;
@eachvec;
// --> end
end
endmodule
//00000000000000000000000000000000000000000000000000000000000000
//仿真验证
//00000000000000000000000000000000000000000000000000000000000000
`timescale 1 ps/ 1 ps
module Serial_parallel_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk=0;
reg in;
reg re;
reg [7:0]in_s;
reg sp_en;
// wires
wire [7:0] o_q;
wire o_p_q;
// assign statements (if any)
Serial_parallel i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.in(in),
.o_q(o_q),
.re(re),
.in_s(in_s),
.sp_en(sp_en),
.o_p_q(o_p_q)
);
parameter s_clk=40000;
integer i;
reg [7:0]s="d";
always #s_clk clk=~clk;
initial
begin
// code that executes only once
// insert code here --> begin
#(s_clk/2) re<=1'b1;
// --> end
$display("Running testbench");
end
always
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin
#(s_clk*2) re<=1'b0;
#(s_clk*2) sp_en<=1'b1;
for(i=0;i<8;i=i+1)begin
// #(s_clk*2) in<=s[8-i];
#(s_clk*2) in<=s[i];
end
in_s=s;
#(s_clk*2) sp_en<=1'b0;
// #(s_clk*2) re<=1'b1;
@eachvec;
// --> end
end
endmodule