module Shift_right(clk,rs,in,out);
input clk;//时钟信号输入端口
input rs;//高电平复位信号端口
input [7:0]in;//数据输入信号端口
output reg[7:0]out;//数据输出信号端口
always@(posedge clk)begin
if(rs)begin//如果复位信号为高电平
out<=8'b0;
end
//否侧右移
else begin
out<={in[0],in[7:1]};//把低位拿走
end
end
endmodule
/
Verilog右移位
/
`timescale 1 ps/ 1 ps
module Shift_right_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk=0;
reg [7:0] in="g";
reg rs;
// wires
wire [7:0] out;
// assign statements (if any)
Shift_right i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.in(in),
.out(out),
.rs(rs)
);
parameter s_clk=2000;
always #(s_clk)clk=~clk;
initial
begin
// code that executes only once
// insert code here --> begin
#(s_clk/5)rs=1'b1;
#(s_clk*2)rs=1'b0;
#(s_clk*2)rs=1'b1;
// --> end
$display("Running testbench");
end
always
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin
@eachvec;
// --> end
end
endmodule