牛客刷题＜15＞优先编码器

最新推荐文章于 2022-08-22 21:25:48 发布

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最新推荐文章于 2022-08-22 21:25:48 发布

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分类专栏： FPGA 文章标签： fpga开发

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题目：优先编码器Ⅰ_牛客题霸_牛客网

分析：题目不难

解法一：I和EI只能作为wire型变量

`timescale 1ns/1ns

module encoder_83(
   input      [7:0]       I   ,
   input                  EI  ,
   
   output wire [2:0]      Y   ,
   output wire            GS  ,
   output wire            EO    
);
    //reg [7:0] I_n;
    //reg       EI_n;
    reg [2:0] Y_n;
    reg       GS_n;
    reg       EO_n;
    always@(EI or I or Y_n or GS_n or EO_n)begin
        if(!EI)begin
            //I = 8'bxxxxxxxx;
            Y_n = 3'b000;
            GS_n = 0;
            EO_n = 0;
        end
        else begin
            //EI = 1;
            if(I==8'b00000000)begin
                Y_n = 3'b000;
                GS_n = 0;
                EO_n = 1;
            end
            else begin
                GS_n = 1;
                EO_n = 0;
        casex(I)
            //8'bxxxxxxxx: Y = 3'b000;
            //8'b00000000: Y = 3'b000;
            8'b1xxxxxxx: Y_n = 3'b111;
            8'b01xxxxxx: Y_n = 3'b110;
            8'b001xxxxx: Y_n = 3'b101;
            8'b0001xxxx: Y_n = 3'b100;
            8'b00001xxx: Y_n = 3'b011;
            8'b000001xx: Y_n = 3'b010;
            8'b0000001x: Y_n = 3'b001;
            8'b00000001: Y_n = 3'b000;
            default: Y_n = 3'b000;
        endcase
            end
        end
    end
    //assign I = I_n;
    //assign EI = EI_n;
    assign Y = Y_n;
    assign GS = GS_n;
    assign EO = EO_n;
endmodule

解法二：

`timescale 1ns/1ns

module encoder_83(
   input      [7:0]       I   ,
   input                  EI  ,
   
   output wire [2:0]      Y   ,
   output wire            GS  ,
   output wire            EO    
);
    //reg [7:0] I_n;
    //reg       EI_n;
    reg [2:0] Y_n;
    reg       GS_n;
    reg       EO_n;
    always@(EI or I or Y_n or GS_n or EO_n)begin
        if(!EI)begin
            Y_n = 3'b000;
            GS_n = 0;
            EO_n = 0;
        end
        else begin
            if(I==8'b00000000)begin
                Y_n = 3'b000;
                GS_n = 0;
                EO_n = 1;
            end
            else begin
        casex(I)
            8'b1xxxxxxx: begin
                Y_n = 3'b111;
                GS_n = 1;
                EO_n = 0;
            end
            8'b01xxxxxx: begin 
                Y_n = 3'b110;
                GS_n = 1;
                EO_n = 0;
            end
            8'b001xxxxx: begin
                Y_n = 3'b101;
                GS_n = 1;
                EO_n = 0;
            end
            8'b0001xxxx: begin
                Y_n = 3'b100;
                GS_n = 1;
                EO_n = 0;
            end
            8'b00001xxx: begin
                Y_n = 3'b011;
                GS_n = 1;
                EO_n = 0;
            end
            8'b000001xx: begin
                Y_n = 3'b010;
                GS_n = 1;
                EO_n = 0;
            end
            8'b0000001x: begin
                Y_n = 3'b001;
                GS_n = 1;
                EO_n = 0;
            end
            8'b00000001: begin
                Y_n = 3'b000;
                GS_n = 1;
                EO_n = 0;
            end
            default: begin
                Y_n = 3'b000;
                GS_n = 0;
                EO_n = 1;
            end
        endcase
            end
        end
    end
    //assign I = I_n;
    //assign EI = EI_n;
    assign Y = Y_n;
    assign GS = GS_n;
    assign EO = EO_n;
endmodule