1.开发要求
1.利用开发版按键输入数据，LCD12864显示数据
2.利用vivado编写代码，利用ila ip核做逻辑分析仪，电脑上显示算法结果
3.LCD12864一行只能显示16个字符，总共4行，前三行分别显示，密钥，明文，密文
2.编写流程
1.先做3个模块 按键输入模块 数据处理模块 LCD12864显示驱动模块
2.在数据处理模块里嵌入一个des算法模块
3.完成项目设计
3.代码展示
1.按键处理模块
通过行列扫描，输出键号，使能
module Array_KeyBoard(
input clk ,
input rstn ,
input [3:0] col ,
output reg [3:0] row ,
output [15:0] key_pulse ,
output reg key_en ,
output reg [3:0] key_data
);
localparam STATE0 = 2'b00;
localparam STATE1 = 2'b01;
localparam STATE2 = 2'b10;
localparam STATE3 = 2'b11;
parameter CNT_200HZ = 60000;
/*
因使用4x4矩阵按键，通过扫描方法实现，所以这里使用状态机实现，共分为4种状态
在其中的某一状态时间里，对应的4个按键相当于独立按键，可按独立按键的周期采样法采样
周期采样时每隔20ms采样一次，对应这里状态机每隔20ms循环一次，每个状态对应5ms时间
*/
//计数器计数分频实现5ms周期信号clk_200hz
reg [15:0] key_out ;
reg [15:0] cnt;
reg clk_200hz;
always@(posedge clk or negedge rstn) begin //复位时计数器cnt清零，clk_200hz信号起始电平为低电平
if(!rstn) begin
cnt <= 16'd0;
clk_200hz <= 1'b0;
end else begin
if(cnt >= ((CNT_200HZ>>1) - 1)) begin //数字逻辑中右移1位相当于除2
cnt <= 16'd0;
clk_200hz <= ~clk_200hz; //clk_200hz信号取反
end else begin
cnt <= cnt + 1'b1;
clk_200hz <= clk_200hz;
end
end
end
reg [1:0] c_state;
//状态机根据clk_200hz信号在4个状态间循环，每个状态对矩阵按键的行接口单行有效
always@(posedge clk_200hz or negedge rstn) begin
if(!rstn) begin
c_state <= STATE0;
row <= 4'b1110;
end else begin
case(c_state)
//状态c_state跳转及对应状态下矩阵按键的row输出
STATE0: begin c_state <= STATE1; row <= 4'b1101; end
STATE1: begin c_state <= STATE2; row <= 4'b1011; end
STATE2: begin c_state <= STATE3; row <= 4'b0111; end
STATE3: begin c_state <= STATE0; row <= 4'b1110; end
default:begin c_state <= STATE0; row <= 4'b1110; end
endcase
end
end
reg [15:0] key,key_r;
//因为每个状态中单行有效，通过对列接口的电平状态采样得到对应4个按键的状态，依次循环
always@(negedge clk_200hz or negedge rstn) begin
if(!rstn) begin
key_out <= 16'hffff; key_r <= 16'hffff; key <= 16'hffff;
end else begin
case(c_state)
//采集当前状态的列数据赋值给对应的寄存器位
//对键盘采样数据进行判定，连续两次采样低电平判定为按键按下
STATE0: begin key_out[ 3: 0] <= key_r[ 3: 0]|key[ 3: 0]; key_r[ 3: 0] <= key[ 3: 0]; key[ 3: 0] <= col; end
STATE1: begin key_out[ 7: 4] <= key_r[ 7: 4]|key[ 7: 4]; key_r[ 7: 4] <= key[ 7: 4]; key[ 7: 4] <= col; end
STATE2: begin key_out[11: 8] <= key_r[11: 8]|key[11: 8]; key_r[11: 8] <= key[11: 8]; key[11: 8] <= col; end
STATE3: begin key_out[15:12] <= key_r[15:12]|key[15:12]; key_r[15:12] <= key[15:12]; key[15:12] <= col; end
default:begin key_out <= 16'hffff; key_r <= 16'hffff; key <= 16'hffff; end
endcase
end
end
reg [15:0] key_out_r;
//Register low_sw_r, lock low_sw to next clk
always @ ( posedge clk or negedge rstn )
if (!rstn) key_out_r <= 16'hffff;
else key_out_r <= key_out; //将前一刻的值延迟锁存
//wire [15:0] key_pulse;
//Detect the negedge of low_sw, generate pulse
assign key_pulse= key_out_r & ( ~key_out); //通过前后两个时刻的值判断
always@(posedge clk or negedge rstn)
begin
if(!rstn)begin
key_en <= 0;
key_data <= 0;
end else begin
case(key_pulse)
16'b0000_0000_0000_0001:begin key_en<=1; key_data<=1; end
16'b0000_0000_0000_0010:begin key_en<=1; key_data<=2; end
16'b0000_0000_0000_0100:begin key_en<=1; key_data<=3; end
16'b0000_0000_0000_1000:begin key_en<=1; key_data<=4'hA; end//shift键，切换字母和数字输出
16'b0000_0000_0001_0000:begin key_en<=1; key_data<=4; end
16'b0000_0000_0010_0000:begin key_en<=1; key_data<=5; end
16'b0000_0000_0100_0000:begin key_en<=1; key_data<=6; end
16'b0000_0000_1000_0000:begin key_en<=1; key_data<=4'hB; end//del键，删除
16'b0000_0001_0000_0000:begin key_en<=1; key_data<=7; end
16'b0000_0010_0000_0000:begin key_en<=1; key_data<=8; end
16'b0000_0100_0000_0000:begin key_en<=1; key_data<=9; end
16'b0000_1000_0000_0000:begin key_en<=1; key_data<=4'hC; end
16'b0001_0000_0000_0000:begin key_en<=1; key_data<=4'hE; end
16'b0010_0000_0000_0000:begin key_en<=1; key_data<=0; end
16'b0100_0000_0000_0000:begin key_en<=1; key_data<=4'hF; end//换行＋输入输出使能
16'h1000_0000_0000_0000:begin key_en<=1; key_data<=4'hD; end
default:begin
key_en <= 0;
end
endcase
end
end
endmodule
最后面是按键功能
分别是0-9，shift ，enter，del，按键
2.数据处理模块
将键号数据处理成LCD12864和des算法模块所需要数据
//数据处理模块
module control(
input clk ,
input clk_100M ,
input clk_100M_180 ,
input rstn ,
input key_en ,
input [3:0] key_data ,
output reg [7:0] data1_1 ,
output reg [7:0] data1_2 ,
output reg [7:0] data1_3 ,
output reg [7:0] data1_4 ,
output reg [7:0] data1_5 ,
output reg [7:0] data1_6 ,
output reg [7:0] data1_7 ,
output reg [7:0] data1_8 ,
output reg [7:0] data1_9 ,
output reg [7:0] data1_10 ,
output reg [7:0] data1_11 ,
output reg [7:0] data1_12 ,
output reg [7:0] data1_13 ,
output reg [7:0] data1_14 ,
output reg [7:0] data1_15 ,
output reg [7:0] data1_16 ,
output reg flag1 ,
output reg [7:0] data2_1 ,
output reg [7:0] data2_2 ,
output reg [7:0] data2_3 ,
output reg [7:0] data2_4 ,
output reg [7:0] data2_5 ,
output reg [7:0] data2_6 ,
output reg [7:0] data2_7 ,
output reg [7:0] data2_8 ,
output reg [7:0] data2_9 ,
output reg [7:0] data2_10 ,
output reg [7:0] data2_11 ,
output reg [7:0] data2_12 ,
output reg [7:0] data2_13 ,
output reg [7:0] data2_14 ,
output reg [7:0] data2_15 ,
output reg [7:0] data2_16 ,
output reg flag2 ,
output reg [7:0] data3_1 ,
output reg [7:0] data3_2 ,
output reg [7:0] data3_3 ,
output reg [7:0] data3_4 ,
output reg [7:0] data3_5 ,
output reg [7:0] data3_6 ,
output reg [7:0] data3_7 ,
output reg [7:0] data3_8 ,
output reg [7:0] data3_9 ,
output reg [7:0] data3_10 ,
output reg [7:0] data3_11 ,
output reg [7:0] data3_12 ,
output reg [7:0] data3_13 ,
output reg [7:0] data3_14 ,
output reg [7:0] data3_15 ,
output reg [7:0] data3_16 ,
output reg flag3
);
reg qie;
always@(posedge clk or negedge rstn)
begin
if(!rstn)begin
qie <= 0;
end else if(key_en && key_data==4'hA)begin
qie <= !qie;
end else begin
qie <= qie;
end
end
reg [3:0] state;//换行状态
always@(posedge clk or negedge rstn)
begin
if(!rstn)begin
state <= 0;
end else begin
case(state)
0:begin
if(key_en && key_data==4'hF)begin
state <= state+1;
end else begin
state <= 0;
end
end
1:begin
if(key_en && key_data==4'hF)begin
state <= 0;
end else begin
state <= state;
end
end
2:begin
if(key_en && key_data==4'hF)begin
state <= 0;
end else begin
state <= state;
end
end
default:
state <= 0;
endcase
end
end
//第一行输出
always@(posedge clk or negedge rstn)
begin
if(!rstn)begin
flag1 <= 0;
end else if(key_en && key_data==4'hF && state==0)begin
flag1 <= 1;
end else begin
flag1 <= 0;
end
end
//第二行输出
always@(posedge clk or negedge rstn)
begin
if(!rstn)begin
flag2 <= 0;
end else if(key_en && key_data==4'hF && state==1)begin
flag2 <= 1;
end else begin
flag2 <= 0;
end
end
//第三行输出
always@(posedge clk or negedge rstn)
begin
if(!rstn)begin
flag3 <= 0;
end else if(key_en && key_data==4'hF && state==2)begin
flag3 <= 1;
end else begin
flag3 <= 0;
end
end
reg [4:0] addr;//shiift和del
always@(posedge clk or negedge rstn)
begin
if(!rstn)begin
addr <= 0;
end else if(key_en && key_data==4'hF)begin
addr <= 0;
end else if(key_en && key_data<4'hA)begin
if(addr >= 16)begin
addr <= 16;
end else begin
addr <= addr+1;
end
end else if(addr>0 && key_en && key_data==4'hB)begin
addr <= addr-1;
end else begin
addr <= addr;
end
end
reg [7:0] data1[15:0];
reg [3:0] dataA[15:0];
reg [4:0] i;
//字母和数字数据处理
always@(posedge clk or negedge rstn)
begin
if(!rstn)begin
for(i=0;i<16;i=i+1)begin
data1[i] <= 0;
dataA[i] <= 0;
end
end else if(key_en && key_data<4'hA && state==0)begin
data1[0] <= qie ? 8'h20+key_data : 8'h10+key_data;
dataA[0] <= qie ? 9+key_data : key_data;
for(i=1;i<16;i=i+1)begin
data1[i] <= data1[i-1];
dataA[i] <= dataA[i-1];
end
end else if(addr>0 && key_en && key_data==4'hB && state==0)begin
for(i=1;i<16;i=i+1)begin
data1[i-1] <= data1[i];
dataA[i-1] <= dataA[i];
end
data1[15] <= 0;
dataA[15] <= 0;
end
end
reg [7:0] data2[15:0];
reg [3:0] dataB[15:0];
reg [4:0] j;
always@(posedge clk or negedge rstn)
begin
if(!rstn)begin
for(j=0;j<16;j=j+1)begin
data2[j] <= 0;
dataB[j] <= 0;
end
end else if(key_en && key_data<4'hA && state==1)begin
data2[0] <= qie ? 8'h20+key_data : 8'h10+key_data;
dataB[0] <= qie ? 9+key_data : key_data;
for(j=1;j<16;j=j+1)begin
data2[j] <= data2[j-1];
dataB[j] <= dataB[j-1];
end
end else if(addr>0 && key_en && key_data==4'hB && state==1)begin
for(j=1;j<16;j=j+1)begin
data2[j-1] <= data2[j];
dataB[j-1] <= dataB[j];
end
data2[15] <= 0;
dataB[15] <= 0;
end
end
reg [7:0] data3[15:0];
reg [3:0] dataC[15:0];
reg [4:0] k;
always@(posedge clk or negedge rstn)
begin
if(!rstn)begin
for(k=0;k<16;k=k+1)begin
data3[k] <= 0;
dataC[k] <= 0;
end
end else if(key_en && key_data<4'hA && state==2)begin
data3[0] <= qie ? 8'h20+key_data : 8'h10+key_data;
dataC[0] <= qie ? 9+key_data : key_data;
for(k=1;k<16;k=k+1)begin
data3[k] <= data3[k-1];
dataC[k] <= dataC[k-1];
end
end else if(addr>0 && key_en && key_data==4'hB && state==2)begin
for(k=1;k<16;k=k+1)begin
data3[k-1] <= data3[k];
dataC[k-1] <= dataC[k];
end
data3[15] <= 0;
dataC[15] <= 0;
end
end
always@(posedge clk)
begin
data1_1 <= data1[15];
data1_2 <= data1[14];
data1_3 <= data1[13];
data1_4 <= data1[12];
data1_5 <= data1[11];
data1_6 <= data1[10];
data1_7 <= data1[9 ];
data1_8 <= data1[8 ];
data1_9 <= data1[7 ];
data1_10 <= data1[6 ];
data1_11 <= data1[5 ];
data1_12 <= data1[4 ];
data1_13 <= data1[3 ];
data1_14 <= data1[2 ];
data1_15 <= data1[1 ];
data1_16 <= data1[0 ];
data2_1 <= data2[15];
data2_2 <= data2[14];
data2_3 <= data2[13];
data2_4 <= data2[12];
data2_5 <= data2[11];
data2_6 <= data2[10];
data2_7 <= data2[9 ];
data2_8 <= data2[8 ];
data2_9 <= data2[7 ];
data2_10 <= data2[6 ];
data2_11 <= data2[5 ];
data2_12 <= data2[4 ];
data2_13 <= data2[3 ];
data2_14 <= data2[2 ];
data2_15 <= data2[1 ];
data2_16 <= data2[0 ];
end
reg [3:0] dataA_1 ;
reg [3:0] dataA_2 ;
reg [3:0] dataA_3 ;
reg [3:0] dataA_4 ;
reg [3:0] dataA_5 ;
reg [3:0] dataA_6 ;
reg [3:0] dataA_7 ;
reg [3:0] dataA_8 ;
reg [3:0] dataA_9 ;
reg [3:0] dataA_10;
reg [3:0] dataA_11;
reg [3:0] dataA_12;
reg [3:0] dataA_13;
reg [3:0] dataA_14;
reg [3:0] dataA_15;
reg [3:0] dataA_16;
reg [3:0] dataB_1 ;
reg [3:0] dataB_2 ;
reg [3:0] dataB_3 ;
reg [3:0] dataB_4 ;
reg [3:0] dataB_5 ;
reg [3:0] dataB_6 ;
reg [3:0] dataB_7 ;
reg [3:0] dataB_8 ;
reg [3:0] dataB_9 ;
reg [3:0] dataB_10;
reg [3:0] dataB_11;
reg [3:0] dataB_12;
reg [3:0] dataB_13;
reg [3:0] dataB_14;
reg [3:0] dataB_15;
reg [3:0] dataB_16;
reg [3:0] dataC_1 ;
reg [3:0] dataC_2 ;
reg [3:0] dataC_3 ;
reg [3:0] dataC_4 ;
reg [3:0] dataC_5 ;
reg [3:0] dataC_6 ;
reg [3:0] dataC_7 ;
reg [3:0] dataC_8 ;
reg [3:0] dataC_9 ;
reg [3:0] dataC_10;
reg [3:0] dataC_11;
reg [3:0] dataC_12;
reg [3:0] dataC_13;
reg [3:0] dataC_14;
reg [3:0] dataC_15;
reg [3:0] dataC_16;
always@(posedge clk)
begin
dataA_1 <= dataA[15];
dataA_2 <= dataA[14];
dataA_3 <= dataA[13];
dataA_4 <= dataA[12];
dataA_5 <= dataA[11];
dataA_6 <= dataA[10];
dataA_7 <= dataA[9 ];
dataA_8 <= dataA[8 ];
dataA_9 <= dataA[7 ];
dataA_10 <= dataA[6 ];
dataA_11 <= dataA[5 ];
dataA_12 <= dataA[4 ];
dataA_13 <= dataA[3 ];
dataA_14 <= dataA[2 ];
dataA_15 <= dataA[1 ];
dataA_16 <= dataA[0 ];
dataB_1 <= dataB[15];
dataB_2 <= dataB[14];
dataB_3 <= dataB[13];
dataB_4 <= dataB[12];
dataB_5 <= dataB[11];
dataB_6 <= dataB[10];
dataB_7 <= dataB[9 ];
dataB_8 <= dataB[8 ];
dataB_9 <= dataB[7 ];
dataB_10 <= dataB[6 ];
dataB_11 <= dataB[5 ];
dataB_12 <= dataB[4 ];
dataB_13 <= dataB[3 ];
dataB_14 <= dataB[2 ];
dataB_15 <= dataB[1 ];
dataB_16 <= dataB[0 ];
dataC_1 <= dataC[15];
dataC_2 <= dataC[14];
dataC_3 <= dataC[13];
dataC_4 <= dataC[12];
dataC_5 <= dataC[11];
dataC_6 <= dataC[10];
dataC_7 <= dataC[9 ];
dataC_8 <= dataC[8 ];
dataC_9 <= dataC[7 ];
dataC_10 <= dataC[6 ];
dataC_11 <= dataC[5 ];
dataC_12 <= dataC[4 ];
dataC_13 <= dataC[3 ];
dataC_14 <= dataC[2 ];
dataC_15 <= dataC[1 ];
dataC_16 <= dataC[0 ];
end
wire i_flag ;
wire [63:0] i_key ;
wire i_key_en ;
wire o_key_ok ;
wire [63:0] i_din ;
wire i_din_en ;
wire [63:0] o_dout ;
wire o_dout_en;
//按键输入数据处理后给des
assign i_key = {dataA_1,dataA_2,dataA_3,dataA_4,dataA_5,dataA_6,dataA_7,dataA_8,dataA_9,dataA_10,dataA_11,dataA_12,dataA_13,dataA_14,dataA_15,dataA_16};
assign i_key_en = flag1;
assign i_din = {dataB_1,dataB_2,dataB_3,dataB_4,dataB_5,dataB_6,dataB_7,dataB_8,dataB_9,dataB_10,dataB_11,dataB_12,dataB_13,dataB_14,dataB_15,dataB_16};
assign i_din_en = flag2;
//链接des模块
des_core des_core_u(
.clk (clk ), //input clk ,
.rst (!rstn ), //input rst ,
.i_flag (1 ), //input i_flag , //1-encrypt,0-decrypt
.i_key (i_key ), //input [63:0] i_key ,
.i_key_en (i_key_en ), //input i_key_en , //1-key init start
.o_key_ok (o_key_ok ), //output o_key_ok , //1-key init done
.i_din (i_din ), //input [63:0] i_din ,
.i_din_en (i_din_en ), //input i_din_en ,
.o_dout (o_dout ), //output [63:0] o_dout ,
.o_dout_en (o_dout_en) //output o_dout_en
);
//DES处理后给LCD12864的数据处理
always@(posedge clk or negedge rstn)
begin
if(!rstn)begin
data3_1 <= 0;
data3_2 <= 0;
data3_3 <= 0;
data3_4 <= 0;
data3_5 <= 0;
data3_6 <= 0;
data3_7 <= 0;
data3_8 <= 0;
data3_9 <= 0;
data3_10 <= 0;
data3_11 <= 0;
data3_12 <= 0;
data3_13 <= 0;
data3_14 <= 0;
data3_15 <= 0;
data3_16 <= 0;
end else if(o_dout_en)begin
data3_1 <= (o_dout[63:60] > 9) ? 8'h17+o_dout[63:60] : 8'h10+o_dout[63:60];
data3_2 <= (o_dout[59:56] > 9) ? 8'h17+o_dout[59:56] : 8'h10+o_dout[59:56];
data3_3 <= (o_dout[55:52] > 9) ? 8'h17+o_dout[55:52] : 8'h10+o_dout[55:52];
data3_4 <= (o_dout[51:48] > 9) ? 8'h17+o_dout[51:48] : 8'h10+o_dout[51:48];
data3_5 <= (o_dout[47:44] > 9) ? 8'h17+o_dout[47:44] : 8'h10+o_dout[47:44];
data3_6 <= (o_dout[43:40] > 9) ? 8'h17+o_dout[43:40] : 8'h10+o_dout[43:40];
data3_7 <= (o_dout[39:36] > 9) ? 8'h17+o_dout[39:36] : 8'h10+o_dout[39:36];
data3_8 <= (o_dout[35:32] > 9) ? 8'h17+o_dout[35:32] : 8'h10+o_dout[35:32];
data3_9 <= (o_dout[31:28] > 9) ? 8'h17+o_dout[31:28] : 8'h10+o_dout[31:28];
data3_10 <= (o_dout[27:24] > 9) ? 8'h17+o_dout[27:24] : 8'h10+o_dout[27:24];
data3_11 <= (o_dout[23:20] > 9) ? 8'h17+o_dout[23:20] : 8'h10+o_dout[23:20];
data3_12 <= (o_dout[19:16] > 9) ? 8'h17+o_dout[19:16] : 8'h10+o_dout[19:16];
data3_13 <= (o_dout[15:12] > 9) ? 8'h17+o_dout[15:12] : 8'h10+o_dout[15:12];
data3_14 <= (o_dout[11:8] > 9) ? 8'h17+o_dout[11:8] : 8'h10+o_dout[11:8] ;
data3_15 <= (o_dout[7:4] > 9) ? 8'h17+o_dout[7:4] : 8'h10+o_dout[7:4] ;
data3_16 <= (o_dout[3:0] > 9) ? 8'h17+o_dout[3:0] : 8'h10+o_dout[3:0] ;
end
end
ila_0 your_instance_name (
.clk(clk_100M),
.probe0(o_dout),
.probe1(i_din),
.probe2(i_key),
.probe3(o_dout_en)
);
在这里面有2个连接的模块，分别是ila和des算法模块
3.LCD12864显示驱动模块
将数据处理成3个使能和8个数据，给硬件显示
module lcd12864(
input clk ,
input rstn ,
input [7:0] data1_1 ,
input [7:0] data1_2 ,
input [7:0] data1_3 ,
input [7:0] data1_4 ,
input [7:0] data1_5 ,
input [7:0] data1_6 ,
input [7:0] data1_7 ,
input [7:0] data1_8 ,
input [7:0] data1_9 ,
input [7:0] data1_10 ,
input [7:0] data1_11 ,
input [7:0] data1_12 ,
input [7:0] data1_13 ,
input [7:0] data1_14 ,
input [7:0] data1_15 ,
input [7:0] data1_16 ,
input [7:0] data2_1 ,
input [7:0] data2_2 ,
input [7:0] data2_3 ,
input [7:0] data2_4 ,
input [7:0] data2_5 ,
input [7:0] data2_6 ,
input [7:0] data2_7 ,
input [7:0] data2_8 ,
input [7:0] data2_9 ,
input [7:0] data2_10 ,
input [7:0] data2_11 ,
input [7:0] data2_12 ,
input [7:0] data2_13 ,
input [7:0] data2_14 ,
input [7:0] data2_15 ,
input [7:0] data2_16 ,
input [7:0] data3_1 ,
input [7:0] data3_2 ,
input [7:0] data3_3 ,
input [7:0] data3_4 ,
input [7:0] data3_5 ,
input [7:0] data3_6 ,
input [7:0] data3_7 ,
input [7:0] data3_8 ,
input [7:0] data3_9 ,
input [7:0] data3_10 ,
input [7:0] data3_11 ,
input [7:0] data3_12 ,
input [7:0] data3_13 ,
input [7:0] data3_14 ,
input [7:0] data3_15 ,
input [7:0] data3_16 ,
output lcd_rs ,
output lcd_rw ,
output lcd_en ,
output [7:0] lcd_data
);
reg clk_lcd;
reg [16:0] cnt ;
always @(posedge clk or negedge rstn)
begin
if(!rstn)begin
cnt <= 17'b0;
clk_lcd <= 0;
end else if(cnt == 17'd7999)begin
cnt <= 17'd0;
clk_lcd <= !clk_lcd;
end else begin
cnt <= cnt +1'b1;
end
end
reg [8:0] state_lcd;
parameter IDLE = 4'd0;
parameter CMD_WIDTH = 4'd1;
parameter CMD_SET = 4'd2;
parameter CMD_CURSOR = 4'd3;
parameter CMD_CLEAR = 4'd4;
parameter CMD_ACCESS = 4'd5;
parameter CMD_DDRAM = 4'd6;
parameter DATA_WRITE = 4'd7;
parameter STOP = 4'd8;
reg lcd_rs_r;
reg [5:0] cnt_time;
reg [7:0] lcd_data_r;
reg [7:0] data_buff;
assign lcd_rs = lcd_rs_r;
assign lcd_rw = 1'b0;
assign lcd_en = clk_lcd;
assign lcd_data = lcd_data_r;
always @(posedge clk_lcd or negedge rstn)
begin
if(!rstn)
begin
lcd_rs_r <= 1'b0;
state_lcd <= IDLE;
lcd_data_r <= 8'bzzzzzzzz;
cnt_time <= 6'd0;
end
else
begin
case(state_lcd)
IDLE:
begin
lcd_rs_r <= 1'b0;
cnt_time <= 6'd0;
state_lcd <= CMD_WIDTH;
lcd_data_r <= 8'bzzzzzzzz;
end
CMD_WIDTH:
begin
lcd_rs_r <= 1'b0;
state_lcd <= CMD_SET;
lcd_data_r <= 8'h30;
end
CMD_SET:
begin
lcd_rs_r <= 1'b0;
state_lcd <= CMD_CURSOR;
lcd_data_r <= 8'h30;
end
CMD_CURSOR:
begin
lcd_rs_r <= 1'b0;
state_lcd <= CMD_CLEAR;
lcd_data_r <= 8'h0c;
end
CMD_CLEAR:
begin
lcd_rs_r <= 1'b0;
state_lcd <= CMD_ACCESS;
lcd_data_r <= 8'h01;
end
CMD_ACCESS:
begin
lcd_rs_r <= 1'b0;
state_lcd <= CMD_DDRAM;
lcd_data_r <= 8'h06;
end
CMD_DDRAM:
begin
lcd_rs_r <= 1'b0;
state_lcd <= DATA_WRITE;
case (cnt_time)
6'd0: lcd_data_r <= 8'h80;
6'd16: lcd_data_r <= 8'h90;
6'd32: lcd_data_r <= 8'h88;
6'd48: lcd_data_r <= 8'h98;
endcase
end
DATA_WRITE:
begin
lcd_rs_r <= 1'b1;
cnt_time <= cnt_time + 1'b1;
lcd_data_r <= data_buff;
case (cnt_time)
6'd15: state_lcd <= CMD_DDRAM;
6'd31: state_lcd <= CMD_DDRAM;
6'd47: state_lcd <= CMD_DDRAM;
6'd63: state_lcd <= STOP;
default:
state_lcd <= DATA_WRITE;
endcase
end
STOP:
begin
lcd_rs_r <= 1'b0;
state_lcd <= CMD_DDRAM;
lcd_data_r <= 8'h80;
cnt_time <= 6'd0;
end
default:
state_lcd <= IDLE;
endcase
end
end
always @(posedge clk)
begin
case (cnt_time)
6'd0: data_buff <= 8'h20 + data1_1 ;
6'd1: data_buff <= 8'h20 + data1_2 ;
6'd2: data_buff <= 8'h20 + data1_3 ;
6'd3: data_buff <= 8'h20 + data1_4 ;
6'd4: data_buff <= 8'h20 + data1_5 ;
6'd5: data_buff <= 8'h20 + data1_6 ;
6'd6: data_buff <= 8'h20 + data1_7 ;
6'd7: data_buff <= 8'h20 + data1_8 ;
6'd8: data_buff <= 8'h20 + data1_9 ;
6'd9: data_buff <= 8'h20 + data1_10;
6'd10: data_buff <= 8'h20 + data1_11;
6'd11: data_buff <= 8'h20 + data1_12;
6'd12: data_buff <= 8'h20 + data1_13;
6'd13: data_buff <= 8'h20 + data1_14;
6'd14: data_buff <= 8'h20 + data1_15;
6'd15: data_buff <= 8'h20 + data1_16;
6'd16: data_buff <= 8'h20 + data2_1 ;
6'd17: data_buff <= 8'h20 + data2_2 ;
6'd18: data_buff <= 8'h20 + data2_3 ;
6'd19: data_buff <= 8'h20 + data2_4 ;
6'd20: data_buff <= 8'h20 + data2_5 ;
6'd21: data_buff <= 8'h20 + data2_6 ;
6'd22: data_buff <= 8'h20 + data2_7 ;
6'd23: data_buff <= 8'h20 + data2_8 ;
6'd24: data_buff <= 8'h20 + data2_9 ;
6'd25: data_buff <= 8'h20 + data2_10;
6'd26: data_buff <= 8'h20 + data2_11;
6'd27: data_buff <= 8'h20 + data2_12;
6'd28: data_buff <= 8'h20 + data2_13;
6'd29: data_buff <= 8'h20 + data2_14;
6'd30: data_buff <= 8'h20 + data2_15;
6'd31: data_buff <= 8'h20 + data2_16;
6'd32: data_buff <= 8'h20 + data3_1 ;
6'd33: data_buff <= 8'h20 + data3_2 ;
6'd34: data_buff <= 8'h20 + data3_3 ;
6'd35: data_buff <= 8'h20 + data3_4 ;
6'd36: data_buff <= 8'h20 + data3_5 ;
6'd37: data_buff <= 8'h20 + data3_6 ;
6'd38: data_buff <= 8'h20 + data3_7 ;
6'd39: data_buff <= 8'h20 + data3_8 ;
6'd40: data_buff <= 8'h20 + data3_9 ;
6'd41: data_buff <= 8'h20 + data3_10;
6'd42: data_buff <= 8'h20 + data3_11;
6'd43: data_buff <= 8'h20 + data3_12;
6'd44: data_buff <= 8'h20 + data3_13;
6'd45: data_buff <= 8'h20 + data3_14;
6'd46: data_buff <= 8'h20 + data3_15;
6'd47: data_buff <= 8'h20 + data3_16;
6'd48: data_buff <= " ";
6'd49: data_buff <= " ";
6'd50: data_buff <= " ";
6'd51: data_buff <= " ";
6'd52: data_buff <= " ";
6'd53: data_buff <= " ";
6'd54: data_buff <= " ";
6'd55: data_buff <= " ";
6'd56: data_buff <= " ";
6'd57: data_buff <= " ";
6'd58: data_buff <= " ";
6'd59: data_buff <= " ";
6'd60: data_buff <= " ";
6'd61: data_buff <= " ";
6'd62: data_buff <= " ";
6'd63: data_buff <= " ";
default : data_buff <= " ";
endcase
end
endmodule 4.des算法模块
这个模块原理不过多解释，网上很多，下面直接展示代码，
代码较多，需要源代码可以加我私聊
//des
module des_core(
input clk ,
input rst ,
input i_flag , //1-encrypt,0-decrypt
input [63:0] i_key ,//
input i_key_en , //1-key init start
output o_key_ok , //1-key init done
input [63:0] i_din ,
input i_din_en ,
output [63:0] o_dout ,
output o_dout_en
);
wire [48*16-1:0] s_exkey;
//key expand
des_keyex u_keyex(
.clk (clk ),
.rst (rst ),
.i_key (i_key ),
.i_key_en (i_key_en ),
.o_exkey (s_exkey ),
.o_key_ok (o_key_ok )
);
//data encrypt or decrypt
des_dpc u_dpc(
.clk (clk ),
.rst (rst ),
.i_flag (i_flag ),
.i_keyex (s_exkey ),
.i_din (i_din ),
.i_din_en (i_din_en ),
.o_dout (o_dout ),
.o_dout_en (o_dout_en )
);
endmodule
//des密钥模块
module des_keyex(
input clk,
input rst,
input [63:0] i_key, //密钥数据
input i_key_en, //密钥数据输入使能，数据完全给1
output [48*16-1:0] o_exkey, //round key
output o_key_ok //密钥输出使能
);
localparam DLY = 0;
wire [55:0] s_key;
wire [55:0] s_lskey;
reg [55:0] r_key;
reg [767:0] r_exkey;
reg [3:0] r_count;
reg r_key_ok;
wire s_busy;
wire [47:0] s_exk;
//parity bit drop//parity bit drop
//奇偶校验位下降
function [55:0] PBD;
input [63:0] D;
begin
PBD[55] = D[64-57];
PBD[54] = D[64-49];
PBD[53] = D[64-41];
PBD[52] = D[64-33];
PBD[51] = D[64-25];
PBD[50] = D[64-17];
PBD[49] = D[64- 9];
PBD[48] = D[64- 1];
PBD[47] = D[64-58];
PBD[46] = D[64-50];
PBD[45] = D[64-42];
PBD[44] = D[64-34];
PBD[43] = D[64-26];
PBD[42] = D[64-18];
PBD[41] = D[64-10];
PBD[40] = D[64- 2];
PBD[39] = D[64-59];
PBD[38] = D[64-51];
PBD[37] = D[64-43];
PBD[36] = D[64-35];
PBD[35] = D[64-27];
PBD[34] = D[64-19];
PBD[33] = D[64-11];
PBD[32] = D[64- 3];
PBD[31] = D[64-60];
PBD[30] = D[64-52];
PBD[29] = D[64-44];
PBD[28] = D[64-36];
PBD[27] = D[64-63];
PBD[26] = D[64-55];
PBD[25] = D[64-47];
PBD[24] = D[64-39];
PBD[23] = D[64-31];
PBD[22] = D[64-23];
PBD[21] = D[64-15];
PBD[20] = D[64- 7];
PBD[19] = D[64-62];
PBD[18] = D[64-54];
PBD[17] = D[64-46];
PBD[16] = D[64-38];
PBD[15] = D[64-30];
PBD[14] = D[64-22];
PBD[13] = D[64-14];
PBD[12] = D[64- 6];
PBD[11] = D[64-61];
PBD[10] = D[64-53];
PBD[ 9] = D[64-45];
PBD[ 8] = D[64-37];
PBD[ 7] = D[64-29];
PBD[ 6] = D[64-21];
PBD[ 5] = D[64-13];
PBD[ 4] = D[64- 5];
PBD[ 3] = D[64-28];
PBD[ 2] = D[64-20];
PBD[ 1] = D[64-12];
PBD[ 0] = D[64- 4];
end
endfunction
//round left shift左移
function [27:0] ROL;
input [27:0] D;
input [1:0] S;
begin
ROL = (S==2'd1) ? {D[26:0],D[27]} : {D[25:0],D[27:26]};
end
endfunction
//CHN: 压缩排列
function [47:0] CEX;
input [55:0] D;
begin
CEX[47] = D[56-14];
CEX[46] = D[56-17];
CEX[45] = D[56-11];
CEX[44] = D[56-24];
CEX[43] = D[56- 1];
CEX[42] = D[56- 5];
CEX[41] = D[56- 3];
CEX[40] = D[56-28];
CEX[39] = D[56-15];
CEX[38] = D[56- 6];
CEX[37] = D[56-21];
CEX[36] = D[56-10];
CEX[35] = D[56-23];
CEX[34] = D[56-19];
CEX[33] = D[56-12];
CEX[32] = D[56- 4];
CEX[31] = D[56-26];
CEX[30] = D[56- 8];
CEX[29] = D[56-16];
CEX[28] = D[56- 7];
CEX[27] = D[56-27];
CEX[26] = D[56-20];
CEX[25] = D[56-13];
CEX[24] = D[56- 2];
CEX[23] = D[56-41];
CEX[22] = D[56-52];
CEX[21] = D[56-31];
CEX[20] = D[56-37];
CEX[19] = D[56-47];
CEX[18] = D[56-55];
CEX[17] = D[56-30];
CEX[16] = D[56-40];
CEX[15] = D[56-51];
CEX[14] = D[56-45];
CEX[13] = D[56-33];
CEX[12] = D[56-48];
CEX[11] = D[56-44];
CEX[10] = D[56-49];
CEX[ 9] = D[56-39];
CEX[ 8] = D[56-56];
CEX[ 7] = D[56-34];
CEX[ 6] = D[56-53];
CEX[ 5] = D[56-46];
CEX[ 4] = D[56-42];
CEX[ 3] = D[56-50];
CEX[ 2] = D[56-36];
CEX[ 1] = D[56-29];
CEX[ 0] = D[56-32];
end
endfunction
assign s_key = i_key_en ? PBD(i_key) : r_key;
//left shift 1|2 bits左移1/2位
assign s_lskey = ((r_count==4'd0)||(r_count==4'd1)||(r_count==4'd8)||(r_count==4'd15)) ? {ROL(s_key[55:28],1),ROL(s_key[27:0],1)} : {ROL(s_key[55:28],2),ROL(s_key[27:0],2)};
assign s_exk = CEX(s_lskey);
always@(posedge clk) begin
if(rst)
r_key <= #DLY 56'b0;
else if(s_busy)
r_key <= #DLY s_lskey;
end
always@(posedge clk) begin
if(rst) begin
r_exkey <= #DLY 768'b0;
end else if(s_busy)begin
r_exkey <= #DLY {r_exkey[48*15-1:0],s_exk};
end
end
always@(posedge clk) begin
if(rst)
r_count <= #DLY 4'd0;
else if(i_key_en)
r_count <= #DLY 4'd1;
else if(r_count!=4'd0)
r_count <= #DLY r_count + 4'd1;
end
assign o_exkey = r_exkey;
assign s_busy = ((r_count!=5'd0)||(i_key_en==1'b1)) ? 1'b1 : 1'b0;
always@(posedge clk or posedge rst) begin
if(rst)
r_key_ok <= #DLY 1'b0;
else if(r_count==4'd15)
r_key_ok <= #DLY 1'b1;
else begin
r_key_ok <= #DLY 1'b0;
end
end
// assign o_key_ok = r_key_ok&(~i_key_en);//输出使能
assign o_key_ok = r_key_ok;
endmodule
//des加解密模块
//接收处理后的密钥，明文数据，输出密文数据
module des_dpc(
input clk,
input rst,
input i_flag,
input [767:0] i_keyex,//密钥
input [63:0] i_din,//明文
input i_din_en,//明文输入确认使能
output [63:0] o_dout,//密文数据
output o_dout_en//密文输出使能
);
localparam DLY = 0;
reg [3:0] r_count;
reg [47:0] r_ka;
wire [31:0] s_y;
wire [31:0] s_z;
wire [47:0] s_za;
wire [31:0] s_zb,s_zc;
reg [31:0] r_y,r_z;
wire [63:0] s_din;
//initial permutation
function [63:0] IEX;
input [63:0] D;
begin
IEX[63] = D[64-58];
IEX[62] = D[64-50];
IEX[61] = D[64-42];
IEX[60] = D[64-34];
IEX[59] = D[64-26];
IEX[58] = D[64-18];
IEX[57] = D[64-10];
IEX[56] = D[64- 2];
IEX[55] = D[64-60];
IEX[54] = D[64-52];
IEX[53] = D[64-44];
IEX[52] = D[64-36];
IEX[51] = D[64-28];
IEX[50] = D[64-20];
IEX[49] = D[64-12];
IEX[48] = D[64- 4];
IEX[47] = D[64-62];
IEX[46] = D[64-54];
IEX[45] = D[64-46];
IEX[44] = D[64-38];
IEX[43] = D[64-30];
IEX[42] = D[64-22];
IEX[41] = D[64-14];
IEX[40] = D[64- 6];
IEX[39] = D[64-64];
IEX[38] = D[64-56];
IEX[37] = D[64-48];
IEX[36] = D[64-40];
IEX[35] = D[64-32];
IEX[34] = D[64-24];
IEX[33] = D[64-16];
IEX[32] = D[64- 8];
IEX[31] = D[64-57];
IEX[30] = D[64-49];
IEX[29] = D[64-41];
IEX[28] = D[64-33];
IEX[27] = D[64-25];
IEX[26] = D[64-17];
IEX[25] = D[64- 9];
IEX[24] = D[64- 1];
IEX[23] = D[64-59];
IEX[22] = D[64-51];
IEX[21] = D[64-43];
IEX[20] = D[64-35];
IEX[19] = D[64-27];
IEX[18] = D[64-19];
IEX[17] = D[64-11];
IEX[16] = D[64- 3];
IEX[15] = D[64-61];
IEX[14] = D[64-53];
IEX[13] = D[64-45];
IEX[12] = D[64-37];
IEX[11] = D[64-29];
IEX[10] = D[64-21];
IEX[ 9] = D[64-13];
IEX[ 8] = D[64- 5];
IEX[ 7] = D[64-63];
IEX[ 6] = D[64-55];
IEX[ 5] = D[64-47];
IEX[ 4] = D[64-39];
IEX[ 3] = D[64-31];
IEX[ 2] = D[64-23];
IEX[ 1] = D[64-15];
IEX[ 0] = D[64- 7];
end
endfunction
//last permutation
function [63:0] LEX;
input [63:0] D;
begin
LEX[63] = D[64-40];
LEX[62] = D[64- 8];
LEX[61] = D[64-48];
LEX[60] = D[64-16];
LEX[59] = D[64-56];
LEX[58] = D[64-24];
LEX[57] = D[64-64];
LEX[56] = D[64-32];
LEX[55] = D[64-39];
LEX[54] = D[64- 7];
LEX[53] = D[64-47];
LEX[52] = D[64-15];
LEX[51] = D[64-55];
LEX[50] = D[64-23];
LEX[49] = D[64-63];
LEX[48] = D[64-31];
LEX[47] = D[64-38];
LEX[46] = D[64- 6];
LEX[45] = D[64-46];
LEX[44] = D[64-14];
LEX[43] = D[64-54];
LEX[42] = D[64-22];
LEX[41] = D[64-62];
LEX[40] = D[64-30];
LEX[39] = D[64-37];
LEX[38] = D[64- 5];
LEX[37] = D[64-45];
LEX[36] = D[64-13];
LEX[35] = D[64-53];
LEX[34] = D[64-21];
LEX[33] = D[64-61];
LEX[32] = D[64-29];
LEX[31] = D[64-36];
LEX[30] = D[64- 4];
LEX[29] = D[64-44];
LEX[28] = D[64-12];
LEX[27] = D[64-52];
LEX[26] = D[64-20];
LEX[25] = D[64-60];
LEX[24] = D[64-28];
LEX[23] = D[64-35];
LEX[22] = D[64- 3];
LEX[21] = D[64-43];
LEX[20] = D[64-11];
LEX[19] = D[64-51];
LEX[18] = D[64-19];
LEX[17] = D[64-59];
LEX[16] = D[64-27];
LEX[15] = D[64-34];
LEX[14] = D[64- 2];
LEX[13] = D[64-42];
LEX[12] = D[64-10];
LEX[11] = D[64-50];
LEX[10] = D[64-18];
LEX[ 9] = D[64-58];
LEX[ 8] = D[64-26];
LEX[ 7] = D[64-33];
LEX[ 6] = D[64- 1];
LEX[ 5] = D[64-41];
LEX[ 4] = D[64- 9];
LEX[ 3] = D[64-49];
LEX[ 2] = D[64-17];
LEX[ 1] = D[64-57];
LEX[ 0] = D[64-25];
end
endfunction
function [47:0] KEX;
input [31:0] D;
begin
//part8
KEX[6*7+5] = D[0];
KEX[6*7+4:6*7+1] = D[4*7+3:4*7];
KEX[6*7+0] = D[4*7-1];
//part7
KEX[6*6+5] = D[4*6+4];
KEX[6*6+4:6*6+1] = D[4*6+3:4*6];
KEX[6*6+0] = D[4*6-1];
//part6
KEX[6*5+5] = D[4*5+4];
KEX[6*5+4:6*5+1] = D[4*5+3:4*5];
KEX[6*5+0] = D[4*5-1];
//part5
KEX[6*4+5] = D[4*4+4];
KEX[6*4+4:6*4+1] = D[4*4+3:4*4];
KEX[6*4+0] = D[4*4-1];
//part4
KEX[6*3+5] = D[4*3+4];
KEX[6*3+4:6*3+1] = D[4*3+3:4*3];
KEX[6*3+0] = D[4*3-1];
//part3
KEX[6*2+5] = D[4*2+4];
KEX[6*2+4:6*2+1] = D[4*2+3:4*2];
KEX[6*2+0] = D[4*2-1];
//part2
KEX[6*1+5] = D[4*1+4];
KEX[6*1+4:6*1+1] = D[4*1+3:4*1];
KEX[6*1+0] = D[4*1-1];
//part1
KEX[6*0+5] = D[4*0+4];
KEX[6*0+4:6*0+1] = D[4*0+3:4*0];
KEX[6*0+0] = D[31];
end
endfunction
function [31:0] DEX;
input [31:0] D;
begin
DEX[31] = D[32-16];
DEX[30] = D[32- 7];
DEX[29] = D[32-20];
DEX[28] = D[32-21];
DEX[27] = D[32-29];
DEX[26] = D[32-12];
DEX[25] = D[32-28];
DEX[24] = D[32-17];
DEX[23] = D[32- 1];
DEX[22] = D[32-15];
DEX[21] = D[32-23];
DEX[20] = D[32-26];
DEX[19] = D[32- 5];
DEX[18] = D[32-18];
DEX[17] = D[32-31];
DEX[16] = D[32-10];
DEX[15] = D[32- 2];
DEX[14] = D[32- 8];
DEX[13] = D[32-24];
DEX[12] = D[32-14];
DEX[11] = D[32-32];
DEX[10] = D[32-27];
DEX[ 9] = D[32- 3];
DEX[ 8] = D[32- 9];
DEX[ 7] = D[32-19];
DEX[ 6] = D[32-13];
DEX[ 5] = D[32-30];
DEX[ 4] = D[32- 6];
DEX[ 3] = D[32-22];
DEX[ 2] = D[32-11];
DEX[ 1] = D[32- 4];
DEX[ 0] = D[32-25];
end
endfunction
always@(posedge clk or posedge rst) begin
if(rst)
r_count <= #DLY 3'b0;
else if(i_din_en)
r_count <= #DLY 3'd1;
else if(r_count!=4'd0)
r_count <= #DLY r_count + 4'd1;
end
always@(*) begin
if(i_flag) begin //encrypt
case(r_count)
4'd00: r_ka = i_keyex[48*16-1:48*15];
4'd01: r_ka = i_keyex[48*15-1:48*14];
4'd02: r_ka = i_keyex[48*14-1:48*13];
4'd03: r_ka = i_keyex[48*13-1:48*12];
4'd04: r_ka = i_keyex[48*12-1:48*11];
4'd05: r_ka = i_keyex[48*11-1:48*10];
4'd06: r_ka = i_keyex[48*10-1:48* 9];
4'd07: r_ka = i_keyex[48* 9-1:48* 8];
4'd08: r_ka = i_keyex[48* 8-1:48* 7];
4'd09: r_ka = i_keyex[48* 7-1:48* 6];
4'd10: r_ka = i_keyex[48* 6-1:48* 5];
4'd11: r_ka = i_keyex[48* 5-1:48* 4];
4'd12: r_ka = i_keyex[48* 4-1:48* 3];
4'd13: r_ka = i_keyex[48* 3-1:48* 2];
4'd14: r_ka = i_keyex[48* 2-1:48* 1];
4'd15: r_ka = i_keyex[48* 1-1:48* 0];
endcase
end else begin //decrypt
case(r_count)
4'd15: r_ka = i_keyex[48*16-1:48*15];
4'd14: r_ka = i_keyex[48*15-1:48*14];
4'd13: r_ka = i_keyex[48*14-1:48*13];
4'd12: r_ka = i_keyex[48*13-1:48*12];
4'd11: r_ka = i_keyex[48*12-1:48*11];
4'd10: r_ka = i_keyex[48*11-1:48*10];
4'd09: r_ka = i_keyex[48*10-1:48* 9];
4'd08: r_ka = i_keyex[48* 9-1:48* 8];
4'd07: r_ka = i_keyex[48* 8-1:48* 7];
4'd06: r_ka = i_keyex[48* 7-1:48* 6];
4'd05: r_ka = i_keyex[48* 6-1:48* 5];
4'd04: r_ka = i_keyex[48* 5-1:48* 4];
4'd03: r_ka = i_keyex[48* 4-1:48* 3];
4'd02: r_ka = i_keyex[48* 3-1:48* 2];
4'd01: r_ka = i_keyex[48* 2-1:48* 1];
4'd00: r_ka = i_keyex[48* 1-1:48* 0];
endcase
end
end
assign s_din = IEX(i_din);
assign s_y = (r_count==3'd0) ? s_din[63:32]:r_y; //left
assign s_z = (r_count==3'd0) ? s_din[31:0]:r_z ; //right
assign s_za = KEX(s_z)^r_ka;
des_sbox1 u_sbox1(.din(s_za[6*8-1:6*7]),.dout(s_zb[4*8-1:4*7]));
des_sbox2 u_sbox2(.din(s_za[6*7-1:6*6]),.dout(s_zb[4*7-1:4*6]));
des_sbox3 u_sbox3(.din(s_za[6*6-1:6*5]),.dout(s_zb[4*6-1:4*5]));
des_sbox4 u_sbox4(.din(s_za[6*5-1:6*4]),.dout(s_zb[4*5-1:4*4]));
des_sbox5 u_sbox5(.din(s_za[6*4-1:6*3]),.dout(s_zb[4*4-1:4*3]));
des_sbox6 u_sbox6(.din(s_za[6*3-1:6*2]),.dout(s_zb[4*3-1:4*2]));
des_sbox7 u_sbox7(.din(s_za[6*2-1:6*1]),.dout(s_zb[4*2-1:4*1]));
des_sbox8 u_sbox8(.din(s_za[6*1-1:6*0]),.dout(s_zb[4*1-1:4*0]));
assign s_zc = DEX(s_zb)^s_y;
always@(posedge clk) begin
r_y <= #DLY s_z;
r_z <= #DLY s_zc;
end
assign o_dout = (r_count==4'd15) ? LEX({s_zc,s_z}):0;//密文数据
assign o_dout_en = (r_count==4'd15) ? 1'b1:1'b0;//密文输出使能
endmodule
`timescale 1ns / 1ps
module des_sbox1(
input [5:0] din,
output [3:0] dout
);
reg [3:0] r_dout;
assign dout = r_dout;
//
always@(din) begin
case({din[5],din[0],din[4:1]})
//line 0
6'h00 : r_dout = 4'd14;
6'h01 : r_dout = 4'd04;
6'h02 : r_dout = 4'd13;
6'h03 : r_dout = 4'd01;
6'h04 : r_dout = 4'd02;
6'h05 : r_dout = 4'd15;
6'h06 : r_dout = 4'd11;
6'h07 : r_dout = 4'd08;
6'h08 : r_dout = 4'd03;
6'h09 : r_dout = 4'd10;
6'h0a : r_dout = 4'd06;
6'h0b : r_dout = 4'd12;
6'h0c : r_dout = 4'd05;
6'h0d : r_dout = 4'd09;
6'h0e : r_dout = 4'd00;
6'h0f : r_dout = 4'd07;
//line 1
6'h10 : r_dout = 4'd00;
6'h11 : r_dout = 4'd15;
6'h12 : r_dout = 4'd07;
6'h13 : r_dout = 4'd04;
6'h14 : r_dout = 4'd14;
6'h15 : r_dout = 4'd02;
6'h16 : r_dout = 4'd13;
6'h17 : r_dout = 4'd01;
6'h18 : r_dout = 4'd10;
6'h19 : r_dout = 4'd06;
6'h1a : r_dout = 4'd12;
6'h1b : r_dout = 4'd11;
6'h1c : r_dout = 4'd09;
6'h1d : r_dout = 4'd05;
6'h1e : r_dout = 4'd03;
6'h1f : r_dout = 4'd08;
//line 2
6'h20 : r_dout = 4'd04;
6'h21 : r_dout = 4'd01;
6'h22 : r_dout = 4'd14;
6'h23 : r_dout = 4'd08;
6'h24 : r_dout = 4'd13;
6'h25 : r_dout = 4'd06;
6'h26 : r_dout = 4'd02;
6'h27 : r_dout = 4'd11;
6'h28 : r_dout = 4'd15;
6'h29 : r_dout = 4'd12;
6'h2a : r_dout = 4'd09;
6'h2b : r_dout = 4'd07;
6'h2c : r_dout = 4'd03;
6'h2d : r_dout = 4'd10;
6'h2e : r_dout = 4'd05;
6'h2f : r_dout = 4'd00;
//line 3
6'h30 : r_dout = 4'd15;
6'h31 : r_dout = 4'd12;
6'h32 : r_dout = 4'd08;
6'h33 : r_dout = 4'd02;
6'h34 : r_dout = 4'd04;
6'h35 : r_dout = 4'd09;
6'h36 : r_dout = 4'd01;
6'h37 : r_dout = 4'd07;
6'h38 : r_dout = 4'd05;
6'h39 : r_dout = 4'd11;
6'h3a : r_dout = 4'd03;
6'h3b : r_dout = 4'd14;
6'h3c : r_dout = 4'd10;
6'h3d : r_dout = 4'd00;
6'h3e : r_dout = 4'd06;
6'h3f : r_dout = 4'd13;
endcase
end
endmodule
`timescale 1ns / 1ps
module des_sbox2(
input [5:0] din,
output [3:0] dout
);
reg [3:0] r_dout;
assign dout = r_dout;
//
always@(din) begin
case({din[5],din[0],din[4:1]})
//line 0
6'h00 : r_dout = 4'd15;
6'h01 : r_dout = 4'd01;
6'h02 : r_dout = 4'd08;
6'h03 : r_dout = 4'd14;
6'h04 : r_dout = 4'd06;
6'h05 : r_dout = 4'd11;
6'h06 : r_dout = 4'd03;
6'h07 : r_dout = 4'd04;
6'h08 : r_dout = 4'd09;
6'h09 : r_dout = 4'd07;
6'h0a : r_dout = 4'd02;
6'h0b : r_dout = 4'd13;
6'h0c : r_dout = 4'd12;
6'h0d : r_dout = 4'd00;
6'h0e : r_dout = 4'd05;
6'h0f : r_dout = 4'd10;
//line 1
6'h10 : r_dout = 4'd03;
6'h11 : r_dout = 4'd13;
6'h12 : r_dout = 4'd04;
6'h13 : r_dout = 4'd07;
6'h14 : r_dout = 4'd15;
6'h15 : r_dout = 4'd02;
6'h16 : r_dout = 4'd08;
6'h17 : r_dout = 4'd14;
6'h18 : r_dout = 4'd12;
6'h19 : r_dout = 4'd00;
6'h1a : r_dout = 4'd01;
6'h1b : r_dout = 4'd10;
6'h1c : r_dout = 4'd06;
6'h1d : r_dout = 4'd09;
6'h1e : r_dout = 4'd11;
6'h1f : r_dout = 4'd05;
//line 2
6'h20 : r_dout = 4'd00;
6'h21 : r_dout = 4'd14;
6'h22 : r_dout = 4'd07;
6'h23 : r_dout = 4'd11;
6'h24 : r_dout = 4'd10;
6'h25 : r_dout = 4'd04;
6'h26 : r_dout = 4'd13;
6'h27 : r_dout = 4'd01;
6'h28 : r_dout = 4'd05;
6'h29 : r_dout = 4'd08;
6'h2a : r_dout = 4'd12;
6'h2b : r_dout = 4'd06;
6'h2c : r_dout = 4'd09;
6'h2d : r_dout = 4'd03;
6'h2e : r_dout = 4'd02;
6'h2f : r_dout = 4'd15;
//line 3
6'h30 : r_dout = 4'd13;
6'h31 : r_dout = 4'd08;
6'h32 : r_dout = 4'd10;
6'h33 : r_dout = 4'd01;
6'h34 : r_dout = 4'd03;
6'h35 : r_dout = 4'd15;
6'h36 : r_dout = 4'd04;
6'h37 : r_dout = 4'd02;
6'h38 : r_dout = 4'd11;
6'h39 : r_dout = 4'd06;
6'h3a : r_dout = 4'd07;
6'h3b : r_dout = 4'd12;
6'h3c : r_dout = 4'd00;
6'h3d : r_dout = 4'd05;
6'h3e : r_dout = 4'd14;
6'h3f : r_dout = 4'd09;
endcase
end
endmodule
`timescale 1ns / 1ps
module des_sbox3(
input [5:0] din,
output [3:0] dout
);
reg [3:0] r_dout;
assign dout = r_dout;
//
always@(din) begin
case({din[5],din[0],din[4:1]})
//line 0
6'h00 : r_dout = 4'd10;
6'h01 : r_dout = 4'd00;
6'h02 : r_dout = 4'd09;
6'h03 : r_dout = 4'd14;
6'h04 : r_dout = 4'd06;
6'h05 : r_dout = 4'd03;
6'h06 : r_dout = 4'd15;
6'h07 : r_dout = 4'd05;
6'h08 : r_dout = 4'd01;
6'h09 : r_dout = 4'd13;
6'h0a : r_dout = 4'd12;
6'h0b : r_dout = 4'd07;
6'h0c : r_dout = 4'd11;
6'h0d : r_dout = 4'd04;
6'h0e : r_dout = 4'd02;
6'h0f : r_dout = 4'd08;
//line 1
6'h10 : r_dout = 4'd13;
6'h11 : r_dout = 4'd07;
6'h12 : r_dout = 4'd00;
6'h13 : r_dout = 4'd09;
6'h14 : r_dout = 4'd03;
6'h15 : r_dout = 4'd04;
6'h16 : r_dout = 4'd06;
6'h17 : r_dout = 4'd10;
6'h18 : r_dout = 4'd02;
6'h19 : r_dout = 4'd08;
6'h1a : r_dout = 4'd05;
6'h1b : r_dout = 4'd14;
6'h1c : r_dout = 4'd12;
6'h1d : r_dout = 4'd11;
6'h1e : r_dout = 4'd15;
6'h1f : r_dout = 4'd01;
//line 2
6'h20 : r_dout = 4'd13;
6'h21 : r_dout = 4'd06;
6'h22 : r_dout = 4'd04;
6'h23 : r_dout = 4'd09;
6'h24 : r_dout = 4'd08;
6'h25 : r_dout = 4'd15;
6'h26 : r_dout = 4'd03;
6'h27 : r_dout = 4'd00;
6'h28 : r_dout = 4'd11;
6'h29 : r_dout = 4'd01;
6'h2a : r_dout = 4'd02;
6'h2b : r_dout = 4'd12;
6'h2c : r_dout = 4'd05;
6'h2d : r_dout = 4'd10;
6'h2e : r_dout = 4'd14;
6'h2f : r_dout = 4'd07;
//line 3
6'h30 : r_dout = 4'd01;
6'h31 : r_dout = 4'd10;
6'h32 : r_dout = 4'd13;
6'h33 : r_dout = 4'd00;
6'h34 : r_dout = 4'd06;
6'h35 : r_dout = 4'd09;
6'h36 : r_dout = 4'd08;
6'h37 : r_dout = 4'd07;
6'h38 : r_dout = 4'd04;
6'h39 : r_dout = 4'd15;
6'h3a : r_dout = 4'd14;
6'h3b : r_dout = 4'd03;
6'h3c : r_dout = 4'd11;
6'h3d : r_dout = 4'd05;
6'h3e : r_dout = 4'd02;
6'h3f : r_dout = 4'd12;
endcase
end
endmodule
`timescale 1ns / 1ps
module des_sbox4(
input [5:0] din,
output [3:0] dout
);
reg [3:0] r_dout;
assign dout = r_dout;
//
always@(din) begin
case({din[5],din[0],din[4:1]})
//line 0
6'h00 : r_dout = 4'd07;
6'h01 : r_dout = 4'd13;
6'h02 : r_dout = 4'd14;
6'h03 : r_dout = 4'd03;
6'h04 : r_dout = 4'd00;
6'h05 : r_dout = 4'd06;
6'h06 : r_dout = 4'd09;
6'h07 : r_dout = 4'd10;
6'h08 : r_dout = 4'd01;
6'h09 : r_dout = 4'd02;
6'h0a : r_dout = 4'd08;
6'h0b : r_dout = 4'd05;
6'h0c : r_dout = 4'd11;
6'h0d : r_dout = 4'd12;
6'h0e : r_dout = 4'd04;
6'h0f : r_dout = 4'd15;
//line 1
6'h10 : r_dout = 4'd13;
6'h11 : r_dout = 4'd08;
6'h12 : r_dout = 4'd11;
6'h13 : r_dout = 4'd05;
6'h14 : r_dout = 4'd06;
6'h15 : r_dout = 4'd15;
6'h16 : r_dout = 4'd00;
6'h17 : r_dout = 4'd03;
6'h18 : r_dout = 4'd04;
6'h19 : r_dout = 4'd07;
6'h1a : r_dout = 4'd02;
6'h1b : r_dout = 4'd12;
6'h1c : r_dout = 4'd01;
6'h1d : r_dout = 4'd10;
6'h1e : r_dout = 4'd14;
6'h1f : r_dout = 4'd09;
//line 2
6'h20 : r_dout = 4'd10;
6'h21 : r_dout = 4'd06;
6'h22 : r_dout = 4'd09;
6'h23 : r_dout = 4'd00;
6'h24 : r_dout = 4'd12;
6'h25 : r_dout = 4'd11;
6'h26 : r_dout = 4'd07;
6'h27 : r_dout = 4'd13;
6'h28 : r_dout = 4'd15;
6'h29 : r_dout = 4'd01;
6'h2a : r_dout = 4'd03;
6'h2b : r_dout = 4'd14;
6'h2c : r_dout = 4'd05;
6'h2d : r_dout = 4'd02;
6'h2e : r_dout = 4'd08;
6'h2f : r_dout = 4'd04;
//line 3
6'h30 : r_dout = 4'd03;
6'h31 : r_dout = 4'd15;
6'h32 : r_dout = 4'd00;
6'h33 : r_dout = 4'd06;
6'h34 : r_dout = 4'd10;
6'h35 : r_dout = 4'd01;
6'h36 : r_dout = 4'd13;
6'h37 : r_dout = 4'd08;
6'h38 : r_dout = 4'd09;
6'h39 : r_dout = 4'd04;
6'h3a : r_dout = 4'd05;
6'h3b : r_dout = 4'd11;
6'h3c : r_dout = 4'd12;
6'h3d : r_dout = 4'd07;
6'h3e : r_dout = 4'd02;
6'h3f : r_dout = 4'd14;
endcase
end
endmodule
`timescale 1ns / 1ps
module des_sbox5(
input [5:0] din,
output [3:0] dout
);
reg [3:0] r_dout;
assign dout = r_dout;
//
always@(din) begin
case({din[5],din[0],din[4:1]})
//line 0
6'h00 : r_dout = 4'd02;
6'h01 : r_dout = 4'd12;
6'h02 : r_dout = 4'd04;
6'h03 : r_dout = 4'd01;
6'h04 : r_dout = 4'd07;
6'h05 : r_dout = 4'd10;
6'h06 : r_dout = 4'd11;
6'h07 : r_dout = 4'd06;
6'h08 : r_dout = 4'd08;
6'h09 : r_dout = 4'd05;
6'h0a : r_dout = 4'd03;
6'h0b : r_dout = 4'd15;
6'h0c : r_dout = 4'd13;
6'h0d : r_dout = 4'd00;
6'h0e : r_dout = 4'd14;
6'h0f : r_dout = 4'd09;
//line 1
6'h10 : r_dout = 4'd14;
6'h11 : r_dout = 4'd11;
6'h12 : r_dout = 4'd02;
6'h13 : r_dout = 4'd12;
6'h14 : r_dout = 4'd04;
6'h15 : r_dout = 4'd07;
6'h16 : r_dout = 4'd13;
6'h17 : r_dout = 4'd01;
6'h18 : r_dout = 4'd05;
6'h19 : r_dout = 4'd00;
6'h1a : r_dout = 4'd15;
6'h1b : r_dout = 4'd10;
6'h1c : r_dout = 4'd03;
6'h1d : r_dout = 4'd09;
6'h1e : r_dout = 4'd08;
6'h1f : r_dout = 4'd06;
//line 2
6'h20 : r_dout = 4'd04;
6'h21 : r_dout = 4'd02;
6'h22 : r_dout = 4'd01;
6'h23 : r_dout = 4'd11;
6'h24 : r_dout = 4'd10;
6'h25 : r_dout = 4'd13;
6'h26 : r_dout = 4'd07;
6'h27 : r_dout = 4'd08;
6'h28 : r_dout = 4'd15;
6'h29 : r_dout = 4'd09;
6'h2a : r_dout = 4'd12;
6'h2b : r_dout = 4'd05;
6'h2c : r_dout = 4'd06;
6'h2d : r_dout = 4'd03;
6'h2e : r_dout = 4'd00;
6'h2f : r_dout = 4'd14;
//line 3
6'h30 : r_dout = 4'd11;
6'h31 : r_dout = 4'd08;
6'h32 : r_dout = 4'd12;
6'h33 : r_dout = 4'd07;
6'h34 : r_dout = 4'd01;
6'h35 : r_dout = 4'd14;
6'h36 : r_dout = 4'd02;
6'h37 : r_dout = 4'd13;
6'h38 : r_dout = 4'd06;
6'h39 : r_dout = 4'd15;
6'h3a : r_dout = 4'd00;
6'h3b : r_dout = 4'd09;
6'h3c : r_dout = 4'd10;
6'h3d : r_dout = 4'd04;
6'h3e : r_dout = 4'd05;
6'h3f : r_dout = 4'd03;
endcase
end
endmodule
`timescale 1ns / 1ps
module des_sbox6(
input [5:0] din,
output [3:0] dout
);
reg [3:0] r_dout;
assign dout = r_dout;
//
always@(din) begin
case({din[5],din[0],din[4:1]})
//line 0
6'h00 : r_dout = 4'd12;
6'h01 : r_dout = 4'd01;
6'h02 : r_dout = 4'd10;
6'h03 : r_dout = 4'd15;
6'h04 : r_dout = 4'd09;
6'h05 : r_dout = 4'd02;
6'h06 : r_dout = 4'd06;
6'h07 : r_dout = 4'd08;
6'h08 : r_dout = 4'd00;
6'h09 : r_dout = 4'd13;
6'h0a : r_dout = 4'd03;
6'h0b : r_dout = 4'd04;
6'h0c : r_dout = 4'd14;
6'h0d : r_dout = 4'd07;
6'h0e : r_dout = 4'd05;
6'h0f : r_dout = 4'd11;
//line 1
6'h10 : r_dout = 4'd10;
6'h11 : r_dout = 4'd15;
6'h12 : r_dout = 4'd04;
6'h13 : r_dout = 4'd02;
6'h14 : r_dout = 4'd07;
6'h15 : r_dout = 4'd12;
6'h16 : r_dout = 4'd09;
6'h17 : r_dout = 4'd05;
6'h18 : r_dout = 4'd06;
6'h19 : r_dout = 4'd01;
6'h1a : r_dout = 4'd13;
6'h1b : r_dout = 4'd14;
6'h1c : r_dout = 4'd00;
6'h1d : r_dout = 4'd11;
6'h1e : r_dout = 4'd03;
6'h1f : r_dout = 4'd08;
//line 2
6'h20 : r_dout = 4'd09;
6'h21 : r_dout = 4'd14;
6'h22 : r_dout = 4'd15;
6'h23 : r_dout = 4'd05;
6'h24 : r_dout = 4'd02;
6'h25 : r_dout = 4'd08;
6'h26 : r_dout = 4'd12;
6'h27 : r_dout = 4'd03;
6'h28 : r_dout = 4'd07;
6'h29 : r_dout = 4'd00;
6'h2a : r_dout = 4'd04;
6'h2b : r_dout = 4'd10;
6'h2c : r_dout = 4'd01;
6'h2d : r_dout = 4'd13;
6'h2e : r_dout = 4'd11;
6'h2f : r_dout = 4'd06;
//line 3
6'h30 : r_dout = 4'd04;
6'h31 : r_dout = 4'd03;
6'h32 : r_dout = 4'd02;
6'h33 : r_dout = 4'd12;
6'h34 : r_dout = 4'd09;
6'h35 : r_dout = 4'd05;
6'h36 : r_dout = 4'd15;
6'h37 : r_dout = 4'd10;
6'h38 : r_dout = 4'd11;
6'h39 : r_dout = 4'd14;
6'h3a : r_dout = 4'd01;
6'h3b : r_dout = 4'd07;
6'h3c : r_dout = 4'd06;
6'h3d : r_dout = 4'd00;
6'h3e : r_dout = 4'd08;
6'h3f : r_dout = 4'd13;
endcase
end
endmodule
`timescale 1ns / 1ps
module des_sbox7(
input [5:0] din,
output [3:0] dout
);
reg [3:0] r_dout;
assign dout = r_dout;
//
always@(din) begin
case({din[5],din[0],din[4:1]})
//line 0
6'h00 : r_dout = 4'd04;
6'h01 : r_dout = 4'd11;
6'h02 : r_dout = 4'd02;
6'h03 : r_dout = 4'd14;
6'h04 : r_dout = 4'd15;
6'h05 : r_dout = 4'd00;
6'h06 : r_dout = 4'd08;
6'h07 : r_dout = 4'd13;
6'h08 : r_dout = 4'd03;
6'h09 : r_dout = 4'd12;
6'h0a : r_dout = 4'd09;
6'h0b : r_dout = 4'd07;
6'h0c : r_dout = 4'd05;
6'h0d : r_dout = 4'd10;
6'h0e : r_dout = 4'd06;
6'h0f : r_dout = 4'd01;
//line 1
6'h10 : r_dout = 4'd13;
6'h11 : r_dout = 4'd00;
6'h12 : r_dout = 4'd11;
6'h13 : r_dout = 4'd07;
6'h14 : r_dout = 4'd04;
6'h15 : r_dout = 4'd09;
6'h16 : r_dout = 4'd01;
6'h17 : r_dout = 4'd10;
6'h18 : r_dout = 4'd14;
6'h19 : r_dout = 4'd03;
6'h1a : r_dout = 4'd05;
6'h1b : r_dout = 4'd12;
6'h1c : r_dout = 4'd02;
6'h1d : r_dout = 4'd15;
6'h1e : r_dout = 4'd08;
6'h1f : r_dout = 4'd06;
//line 2
6'h20 : r_dout = 4'd01;
6'h21 : r_dout = 4'd04;
6'h22 : r_dout = 4'd11;
6'h23 : r_dout = 4'd13;
6'h24 : r_dout = 4'd12;
6'h25 : r_dout = 4'd03;
6'h26 : r_dout = 4'd07;
6'h27 : r_dout = 4'd14;
6'h28 : r_dout = 4'd10;
6'h29 : r_dout = 4'd15;
6'h2a : r_dout = 4'd06;
6'h2b : r_dout = 4'd08;
6'h2c : r_dout = 4'd00;
6'h2d : r_dout = 4'd05;
6'h2e : r_dout = 4'd09;
6'h2f : r_dout = 4'd02;
//line 3
6'h30 : r_dout = 4'd06;
6'h31 : r_dout = 4'd11;
6'h32 : r_dout = 4'd13;
6'h33 : r_dout = 4'd08;
6'h34 : r_dout = 4'd01;
6'h35 : r_dout = 4'd04;
6'h36 : r_dout = 4'd10;
6'h37 : r_dout = 4'd07;
6'h38 : r_dout = 4'd09;
6'h39 : r_dout = 4'd05;
6'h3a : r_dout = 4'd00;
6'h3b : r_dout = 4'd15;
6'h3c : r_dout = 4'd14;
6'h3d : r_dout = 4'd02;
6'h3e : r_dout = 4'd03;
6'h3f : r_dout = 4'd12;
endcase
end
endmodule
`timescale 1ns / 1ps
module des_sbox8(
input [5:0] din,
output [3:0] dout
);
reg [3:0] r_dout;
assign dout = r_dout;
//
always@(din) begin
case({din[5],din[0],din[4:1]})
//line 0
6'h00 : r_dout = 4'd13;
6'h01 : r_dout = 4'd02;
6'h02 : r_dout = 4'd08;
6'h03 : r_dout = 4'd04;
6'h04 : r_dout = 4'd06;
6'h05 : r_dout = 4'd15;
6'h06 : r_dout = 4'd11;
6'h07 : r_dout = 4'd01;
6'h08 : r_dout = 4'd10;
6'h09 : r_dout = 4'd09;
6'h0a : r_dout = 4'd03;
6'h0b : r_dout = 4'd14;
6'h0c : r_dout = 4'd05;
6'h0d : r_dout = 4'd00;
6'h0e : r_dout = 4'd12;
6'h0f : r_dout = 4'd07;
//line 1
6'h10 : r_dout = 4'd01;
6'h11 : r_dout = 4'd15;
6'h12 : r_dout = 4'd13;
6'h13 : r_dout = 4'd08;
6'h14 : r_dout = 4'd10;
6'h15 : r_dout = 4'd03;
6'h16 : r_dout = 4'd07;
6'h17 : r_dout = 4'd04;
6'h18 : r_dout = 4'd12;
6'h19 : r_dout = 4'd05;
6'h1a : r_dout = 4'd06;
6'h1b : r_dout = 4'd11;
6'h1c : r_dout = 4'd00;
6'h1d : r_dout = 4'd14;
6'h1e : r_dout = 4'd09;
6'h1f : r_dout = 4'd02;
//line 2
6'h20 : r_dout = 4'd07;
6'h21 : r_dout = 4'd11;
6'h22 : r_dout = 4'd04;
6'h23 : r_dout = 4'd01;
6'h24 : r_dout = 4'd09;
6'h25 : r_dout = 4'd12;
6'h26 : r_dout = 4'd14;
6'h27 : r_dout = 4'd02;
6'h28 : r_dout = 4'd00;
6'h29 : r_dout = 4'd06;
6'h2a : r_dout = 4'd10;
6'h2b : r_dout = 4'd13;
6'h2c : r_dout = 4'd15;
6'h2d : r_dout = 4'd03;
6'h2e : r_dout = 4'd05;
6'h2f : r_dout = 4'd08;
//line 3
6'h30 : r_dout = 4'd02;
6'h31 : r_dout = 4'd01;
6'h32 : r_dout = 4'd14;
6'h33 : r_dout = 4'd07;
6'h34 : r_dout = 4'd04;
6'h35 : r_dout = 4'd10;
6'h36 : r_dout = 4'd08;
6'h37 : r_dout = 4'd13;
6'h38 : r_dout = 4'd15;
6'h39 : r_dout = 4'd12;
6'h3a : r_dout = 4'd09;
6'h3b : r_dout = 4'd00;
6'h3c : r_dout = 4'd03;
6'h3d : r_dout = 4'd05;
6'h3e : r_dout = 4'd06;
6'h3f : r_dout = 4'd11;
endcase
end
endmodule
以上是des算法模块
在des算法模块里有密钥计算，明文加密2个模块，明文加密里面有8个小模块
5.top
module top(
input sysclkin ,
input button ,
input [3:0] col ,
output [3:0] row ,
output lcd_rs ,
output lcd_rw ,
output lcd_en ,
output [7:0] lcd_data
);
wire clk_100M;
wire clk_100M_180;
//========clk_wiz_0========
clk_wiz_0 clk_wiz_0_0
(
.clk_out1(clk_100M), // output clk_out1
.clk_in1(sysclkin) // input clk_in1
);
wire [15:0] key_pulse;
wire key_en ;
wire [7:0] key_data ;
wire [7:0] data1_1 ;
wire [7:0] data1_2 ;
wire [7:0] data1_3 ;
wire [7:0] data1_4 ;
wire [7:0] data1_5 ;
wire [7:0] data1_6 ;
wire [7:0] data1_7 ;
wire [7:0] data1_8 ;
wire [7:0] data1_9 ;
wire [7:0] data1_10 ;
wire [7:0] data1_11 ;
wire [7:0] data1_12 ;
wire [7:0] data1_13 ;
wire [7:0] data1_14 ;
wire [7:0] data1_15 ;
wire [7:0] data1_16 ;
wire [7:0] data2_1 ;
wire [7:0] data2_2 ;
wire [7:0] data2_3 ;
wire [7:0] data2_4 ;
wire [7:0] data2_5 ;
wire [7:0] data2_6 ;
wire [7:0] data2_7 ;
wire [7:0] data2_8 ;
wire [7:0] data2_9 ;
wire [7:0] data2_10 ;
wire [7:0] data2_11 ;
wire [7:0] data2_12 ;
wire [7:0] data2_13 ;
wire [7:0] data2_14 ;
wire [7:0] data2_15 ;
wire [7:0] data2_16 ;
wire [7:0] data3_1 ;
wire [7:0] data3_2 ;
wire [7:0] data3_3 ;
wire [7:0] data3_4 ;
wire [7:0] data3_5 ;
wire [7:0] data3_6 ;
wire [7:0] data3_7 ;
wire [7:0] data3_8 ;
wire [7:0] data3_9 ;
wire [7:0] data3_10 ;
wire [7:0] data3_11 ;
wire [7:0] data3_12 ;
wire [7:0] data3_13 ;
wire [7:0] data3_14 ;
wire [7:0] data3_15 ;
wire [7:0] data3_16 ;
wire flag1 ;
wire flag2 ;
wire flag3 ;
Array_KeyBoard Array_KeyBoard_u(
.clk (sysclkin ), //input clk ,
.rstn (button ), //input rstn ,
.col (col ), //input [3:0] col ,
.row (row ), //output reg [3:0] row ,
.key_pulse (key_pulse), //output [15:0] key_pulse ,
.key_en (key_en ), //output reg key_en ,
.key_data (key_data ) //output reg [3:0] key_data
);
control control_u(
.clk_100M(clk_100M), // output clk_out1
.clk (sysclkin ), //input clk ,
.rstn (button ), //input rstn ,
.key_en (key_en ), //input key_en ,
.key_data (key_data ), //input [3:0] key_data ,
.data1_1 (data1_1 ), //output reg [3:0] data1_1 ,
.data1_2 (data1_2 ), //output reg [3:0] data1_2 ,
.data1_3 (data1_3 ), //output reg [3:0] data1_3 ,
.data1_4 (data1_4 ), //output reg [3:0] data1_4 ,
.data1_5 (data1_5 ), //output reg [3:0] data1_5 ,
.data1_6 (data1_6 ), //output reg [3:0] data1_6 ,
.data1_7 (data1_7 ), //output reg [3:0] data1_7 ,
.data1_8 (data1_8 ), //output reg [3:0] data1_8 ,
.data1_9 (data1_9 ), //output reg [3:0] data1_9 ,
.data1_10 (data1_10 ), //output reg [3:0] data1_10 ,
.data1_11 (data1_11 ), //output reg [3:0] data1_11 ,
.data1_12 (data1_12 ), //output reg [3:0] data1_12 ,
.data1_13 (data1_13 ), //output reg [3:0] data1_13 ,
.data1_14 (data1_14 ), //output reg [3:0] data1_14 ,
.data1_15 (data1_15 ), //output reg [3:0] data1_15 ,
.data1_16 (data1_16 ), //output reg [3:0] data1_16 ,
.flag1 (flag1 ), //output reg flag1 ,
.data2_1 (data2_1 ), //output reg [3:0] data2_1 ,
.data2_2 (data2_2 ), //output reg [3:0] data2_2 ,
.data2_3 (data2_3 ), //output reg [3:0] data2_3 ,
.data2_4 (data2_4 ), //output reg [3:0] data2_4 ,
.data2_5 (data2_5 ), //output reg [3:0] data2_5 ,
.data2_6 (data2_6 ), //output reg [3:0] data2_6 ,
.data2_7 (data2_7 ), //output reg [3:0] data2_7 ,
.data2_8 (data2_8 ), //output reg [3:0] data2_8 ,
.data2_9 (data2_9 ), //output reg [3:0] data2_9 ,
.data2_10 (data2_10 ), //output reg [3:0] data2_10 ,
.data2_11 (data2_11 ), //output reg [3:0] data2_11 ,
.data2_12 (data2_12 ), //output reg [3:0] data2_12 ,
.data2_13 (data2_13 ), //output reg [3:0] data2_13 ,
.data2_14 (data2_14 ), //output reg [3:0] data2_14 ,
.data2_15 (data2_15 ), //output reg [3:0] data2_15 ,
.data2_16 (data2_16 ), //output reg [3:0] data2_16 ,
.flag2 (flag2 ), //output reg flag2 ,
.data3_1 (data3_1 ), //output reg [3:0] data3_1 ,
.data3_2 (data3_2 ), //output reg [3:0] data3_2 ,
.data3_3 (data3_3 ), //output reg [3:0] data3_3 ,
.data3_4 (data3_4 ), //output reg [3:0] data3_4 ,
.data3_5 (data3_5 ), //output reg [3:0] data3_5 ,
.data3_6 (data3_6 ), //output reg [3:0] data3_6 ,
.data3_7 (data3_7 ), //output reg [3:0] data3_7 ,
.data3_8 (data3_8 ), //output reg [3:0] data3_8 ,
.data3_9 (data3_9 ), //output reg [3:0] data3_9 ,
.data3_10 (data3_10 ), //output reg [3:0] data3_10 ,
.data3_11 (data3_11 ), //output reg [3:0] data3_11 ,
.data3_12 (data3_12 ), //output reg [3:0] data3_12 ,
.data3_13 (data3_13 ), //output reg [3:0] data3_13 ,
.data3_14 (data3_14 ), //output reg [3:0] data3_14 ,
.data3_15 (data3_15 ), //output reg [3:0] data3_15 ,
.data3_16 (data3_16 ), //output reg [3:0] data3_16 ,
.flag3 (flag3 ) //output reg flag3
);
lcd12864 lcd12864_u(
.clk (sysclkin ), //input clk ,
.rstn (button ), //input rstn ,
.data1_1 (data1_1 ), //input [3:0] data1_1 ,
.data1_2 (data1_2 ), //input [3:0] data1_2 ,
.data1_3 (data1_3 ), //input [3:0] data1_3 ,
.data1_4 (data1_4 ), //input [3:0] data1_4 ,
.data1_5 (data1_5 ), //input [3:0] data1_5 ,
.data1_6 (data1_6 ), //input [3:0] data1_6 ,
.data1_7 (data1_7 ), //input [3:0] data1_7 ,
.data1_8 (data1_8 ), //input [3:0] data1_8 ,
.data1_9 (data1_9 ), //input [3:0] data1_9 ,
.data1_10 (data1_10), //input [3:0] data1_10 ,
.data1_11 (data1_11), //input [3:0] data1_11 ,
.data1_12 (data1_12), //input [3:0] data1_12 ,
.data1_13 (data1_13), //input [3:0] data1_13 ,
.data1_14 (data1_14), //input [3:0] data1_14 ,
.data1_15 (data1_15), //input [3:0] data1_15 ,
.data1_16 (data1_16), //input [3:0] data1_16 ,
.data2_1 (data2_1 ), //input [3:0] data2_1 ,
.data2_2 (data2_2 ), //input [3:0] data2_2 ,
.data2_3 (data2_3 ), //input [3:0] data2_3 ,
.data2_4 (data2_4 ), //input [3:0] data2_4 ,
.data2_5 (data2_5 ), //input [3:0] data2_5 ,
.data2_6 (data2_6 ), //input [3:0] data2_6 ,
.data2_7 (data2_7 ), //input [3:0] data2_7 ,
.data2_8 (data2_8 ), //input [3:0] data2_8 ,
.data2_9 (data2_9 ), //input [3:0] data2_9 ,
.data2_10 (data2_10), //input [3:0] data2_10 ,
.data2_11 (data2_11), //input [3:0] data2_11 ,
.data2_12 (data2_12), //input [3:0] data2_12 ,
.data2_13 (data2_13), //input [3:0] data2_13 ,
.data2_14 (data2_14), //input [3:0] data2_14 ,
.data2_15 (data2_15), //input [3:0] data2_15 ,
.data2_16 (data2_16), //input [3:0] data2_16 ,
.data3_1 (data3_1 ), //input [3:0] data3_1 ,//0-9 +8'h10 a-f +8'h11;
.data3_2 (data3_2 ), //input [3:0] data3_2 ,//0-9 +8'h10 a-f +8'h11;
.data3_3 (data3_3 ), //input [3:0] data3_3 ,//0-9 +8'h10 a-f +8'h11;
.data3_4 (data3_4 ), //input [3:0] data3_4 ,//0-9 +8'h10 a-f +8'h11;
.data3_5 (data3_5 ), //input [3:0] data3_5 ,//0-9 +8'h10 a-f +8'h11;
.data3_6 (data3_6 ), //input [3:0] data3_6 ,//0-9 +8'h10 a-f +8'h11;
.data3_7 (data3_7 ), //input [3:0] data3_7 ,//0-9 +8'h10 a-f +8'h11;
.data3_8 (data3_8 ), //input [3:0] data3_8 ,//0-9 +8'h10 a-f +8'h11;
.data3_9 (data3_9 ), //input [3:0] data3_9 ,//0-9 +8'h10 a-f +8'h11;
.data3_10 (data3_10), //input [3:0] data3_10 ,//0-9 +8'h10 a-f +8'h11;
.data3_11 (data3_11), //input [3:0] data3_11 ,//0-9 +8'h10 a-f +8'h11;
.data3_12 (data3_12), //input [3:0] data3_12 ,//0-9 +8'h10 a-f +8'h11;
.data3_13 (data3_13), //input [3:0] data3_13 ,//0-9 +8'h10 a-f +8'h11;
.data3_14 (data3_14), //input [3:0] data3_14 ,//0-9 +8'h10 a-f +8'h11;
.data3_15 (data3_15), //input [3:0] data3_15 ,//0-9 +8'h10 a-f +8'h11;
.data3_16 (data3_16), //input [3:0] data3_16 ,//0-9 +8'h10 a-f +8'h11;
.lcd_rs (lcd_rs ), //output lcd_rs ,
.lcd_rw (lcd_rw ), //output lcd_rw ,
.lcd_en (lcd_en ), //output lcd_en ,
.lcd_data (lcd_data) //output [7:0] lcd_data
);
endmodule
4.总结
本设计能在LCD12864上显示16个密钥，16个明文，16个密文
需要vivado源代码私我
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