FPGA配合R820T

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                <p>想法：<a href="https://so.csdn.net/so/search?q=FPGA&amp;spm=1001.2101.3001.7020" target="_blank" class="hl hl-1" data-report-click="{&quot;spm&quot;:&quot;1001.2101.3001.7020&quot;,&quot;dest&quot;:&quot;https://so.csdn.net/so/search?q=FPGA&amp;spm=1001.2101.3001.7020&quot;,&quot;extra&quot;:&quot;{\&quot;searchword\&quot;:\&quot;FPGA\&quot;}&quot;}" data-tit="FPGA" data-pretit="fpga" rel="noopener nofollow">FPGA</a>控制R820T的I2C，将R820T输出的中频做处理。</p> 

准备：某宝买的RTL-SDR，原理如下：

软件无线电通过数字信号处理来实现无线信号的调制解调。在RTL-SDR中通过调谐芯片(R820T、E4000)将无线信号下变频至低中频信号，由RTL2832U中的ADC采样得到数字信号，再进行数字下变频得到基带信号，由USB传送给计算机。RTL-SDR得到的基带信号是I/Q信号交错排列的形式，计算机对基带信号进行分离得到两路信号即I/Q信号进行解调。

硬件原理图大致如下图所示：

把RTL2832U取下来，将SDA、SCL、IF_P、IF_N引出，

R820T结构图

因为配置R820T的比较复杂，使用zynq+axi-iic方式完成R820T的控制，资源够的话，例化Microblaze也是可以的。

这里提供R820T的手册下载百度云盘链接

链接：https://pan.baidu.com/s/1BWMHACYQsdAqvp5c7cLlGw 
提取码：5aci 

R820T中比较重要的寄存器：

/* Those initial values start from REG_SHADOW_START */
static const uint8_t r82xx_init_array[NUM_REGS] = {
    0x83, 0x32, 0x75,            /* 05 to 07 */
    0xc0, 0x40, 0xd6, 0x6c,            /* 08 to 0b */
    0xf5, 0x63, 0x75, 0x68,            /* 0c to 0f */
    0x6c, 0x83, 0x80, 0x00,            /* 10 to 13 */
    0x0f, 0x00, 0xc0, 0x30,            /* 14 to 17 */
    0x48, 0xcc, 0x60, 0x00,            /* 18 to 1b */
    0x54, 0xae, 0x4a, 0xc0            /* 1c to 1f */
};
------------R5=0x83---------------
[7]Loop through ON/OFF = off
[5]LNA 1 power control = on
[4]LNA gain mode switch = on
[3:0]LNA manual gain control = 0011
------------R6=0x32--------------
[7]Power detector 1 on/off = on
[6]Power detector 3 on/off = off
[5]Filter gain 3db = +3db
[2:0]LNA power control = 010
------------R7=0x75---------------
[6]Mixer power = on
[5]Mixer current control = normal current
[4]Mixer gain mode = auto mode
[3:0]Mixer manual gain control = 0101
------------R8=0xc0---------------
[7]Mixer buffer power on/off = on
[6]Mixer buffer current setting = low current
[5:0]Image Gain Adjustment = 0
------------R9=0x40----------------
[7]IF Filter power on/off = filter on
[6]IF Filter current = low current
[5:0]Image Phase Adjustment = 0
------------R10=0xd6--------------
[7]Filter power on/off = on
[6:5]Filter power control = 10
[4] 1
[3:0]Filter bandwidth manual fine tune = 0110
------------R11=0x6c----------------
[7] 0
[6:5]Filter bandwidth manual course tunnel = middle
[4] 0
[3:0]High pass filter corner control = 1100
------------R12=0xf5-------------
[6]VGA power control = vga power on
[4]VGA GAIN manual / pin selector = IF vga gain controlled by vagc pin
[3:0]IF vga manual gain control = 0101
------------R13=0x63--------------
[7:4]LNA agc power detector voltage threshold high setting = 0110
[3:0]LNA agc power detector voltage threshold low setting = 0011
------------R14=0x75--------------
[7:4]MIXER agc power detector voltage threshold high setting = 0111
[3:0]MIXER agc power detector voltage threshold low setting = 0110
------------R15=0x68---------------
[4]Clock out pin control = clk output on
[1]AGC clk control = internal agc clock on
------------R16=0x6c----------------
[7:5]PLL to Mixer divider number control = mixer in = vco out
[4]PLL Reference frequency Divider = fref=xtal_freq
[1:0]Internal xtal cap setting = no cap
------------R17=0x83--------------
[7:6]PLL analog low drop out regulator switch = 2.0V
------------R18=0x80---------------
[7:6]PLL integer divider number input Si2c = 10
[5:0]PLL integer divider number input Ni2c = 0
--------------------------------------
------------R30=0x4a------------------
[5:0]Power detector timing control = 001010
[6]Filter extension under weak signal = Enable
 
 

  
  
 
 
 
 

R820T和RTL2382U驱动可以在这里下载：https://github.com/osmocom/rtl-sdr.git:  Software to turn the RTL2832U into a SDR receiver
控制R820T只需要其中的tuner_r82xx.c、tuner_r82xx.h、librtlsdr.c、librtlsdr.h、rtl-sdr.h，略加修改删除其中的配置RTL2832U部分；

示波器采集到R820T I通道输出

FFT波形：

因为没有较好的模数转换器，使用LVDS 1-bit采样法，采集R820T I通道输出，FPGA采集到波形：

在Matlab上做算法验证：

clear
clc
f1=1*1000;       %信号频率为1KHz

f2=1010001000; %信号频率为10MHz
Fs=24010001000; %采样频率为200MHz
C=3; %滤波器级数

%%%%%%%%%%%%%%%%%%FM调制%%%%%%%%%%%%%%%%%%%%%
% Fs = 24010^6; % 240M采样率
am = 255; % 设定调制信号幅度
% f1 = 1010^3; % 调制信号频率10K
% f0 = 10*10^6; % 载波频率10M
dt = 1/Fs; % 采样间隔
t=0:dt:f2/Fs;
N=length(t);

mt = amsin(2pif1t); % 生成调制信号 10K
ct = cos(2pif2*t); % 生成载波 10M
kf = 10; % 调频系数 频偏75kHz
figure(3);
subplot(411);plot(mt);title(‘Matlab仿真滤波前信号波形’);

integral_mt(1)=0;
for i=1:length(t)-1 %积分
integral_mt(i+1)=integral_mt(i)+mt(i)dt;
end
%figure(100);plot(t,integral_mt); title(‘integral_mt’);
sfm = cos(2pif2t+2pikf*integral_mt); %已调信号
for i=1:length(sfm)
if(sfm(i)>0)
sfm(i) = 1;
else
sfm(i) = -1;
end
end
figure(3);
subplot(412);plot(sfm);title(‘Matlab仿真滤波前信号波形’);

st=sin(2pif2t); %提取载波的正交分量 sin(wct)
ct=cos(2pif2t); %cos(wct)
for i=1:length(sfm)
If(i)=sfm(i)*ct(i);
Qf(i)=sfm(i)*st(i);
end
figure(1);
subplot(211);plot(If); title(“If”);
subplot(212);plot(Qf); title(“Qf”);

% Flp=f2;
% b=fir1(200,Flp/Fs,‘low’); %设计滤波器
% Im=filter(b,1,If);
% Qm=filter(b,1,Qf);
% figure(2);
% subplot(321);plot(Im); title(“Im”);
% subplot(322);plot(Qm); title(“Qm”);

If1=cic1(5, If);
Qf1=cic1(5, Qf);
figure(2);
subplot(323);plot(If1(1:length(Qf1)-3)); title(“If1”);
subplot(324);plot(Qf1(1:length(Qf1)-3)); title(“Qf1”);

If2=cic1(50, If1(1:length(If1)-3));
Qf2=cic1(50, Qf1(1:length(Qf1)-3));
figure(2);
subplot(325);plot(If2(1:length(If2)-3)); title(“If2”);
subplot(326);plot(Qf2(1:length(Qf2)-3)); title(“Qf2”);

%%%%%%%%%%%%%进行16bit量化%%%%%%%%%%%%%%%%%
If16=round(If2/max(abs(If2(1:length(If2)-3)))(2^15-1));
Qf16=round(Qf2/max(abs(Qf2(1:length(Qf2)-3)))(2^15-1));
%求系数绝对值之和，以此估计滤波后的有效数据位宽
% sum_Shape=sum(abs(Qf16));
%%%%%%%%%%%%%%%%%%%解调%%%%%%%%%%%%%%%%%%%
Sn(1)=0;
for i=2:length(If16)
Sn(i) =-(Qf16(i)*If16(i-1)-Qf16(i-1)*If16(i));
end
Sn=Sn/max(abs(Sn));
Sn1=cic1(50, Sn);
figure(3);
subplot(413);
plot(Sn1(10:length(Sn1)-3));title(‘解调信号波形’);

将Matlab调制后波形输出到FPGA仿真模型中，使用modelsim仿真波形，经过1bit采样、正交解调和3级CIC滤波后的波形总是杂乱无章，反复修改参数，关键在于CIC滤波抽取间隔值不能太大，目前大约在5~10之间。

目前没有DA模块，在FPGA综合实现后，无法验证输出是否正确，故暂停。