sv compiler directive define

In Verilog, the ‘define macro text can include a backslash ( \ ) at the end of a line to show continuation on the next line.
In SystemVerilog, the macro text can also include

`",      `\`"     and     ``    .

An

`"

overrides the usual lexical meaning of ", and indicates that the expansion should include an actual quotation mark. This allows string literals to be constructed from macro arguments.
A \" indicates that the expansion should include the escape sequence ", e.g.

`define msg(x,y) `"x: `\`"y`\`"`"

This expands:

$display(`msg(left side,right side));

to:

$display("left side: \"right side\"");

A `` delimits lexical tokens without introducing white space, allowing identifiers to be constructed from arguments,
e.g.

`define foo(f) a_``f``_suffix

This expands:

‘foo(bar)

to:

a_bar_suffix

另一个实际的例子：

`define BUS_2_CFG(chl_num)  \
    begin     \
        case(ahb_trans.haddr[5:0])     \
            6'h00: i_chl_cfg.reg_cfg[``chl_num``].srcaddr  =  ahb_trans.hwdata;     \
            6'h04: i_chl_cfg.reg_cfg[``chl_num``].destaddr =  ahb_trans.hwdata;     \
        endcase  \
    end  \
    

case (ahb_trans.haddr[31:6])
    26'd00: `BUS_2_CFG(0)
endcase