Verilog编译指令（Compiler directives）

Verilog编译指令（Compiler directives）

Compiler directives are instructions to the Verilog compiler.

Syntax:

`celldefine
  module_declaration
`endcelldefine
`default_nettype net_data_type
`define macro_name [ (argument, ...) ] text
`undef macro_name
`ifdef macro_name | `ifndef macro_name
  verilog_code
[ `elsif macro_name
  verilog_code ]
[ `else
  verilog_code ]
`endif
`include "file_name"
`reset_all
`timescale unit base/precision base
`line line_number "file_name" level

Description:

Compiler directives begin with the grave accent ` and do not end with a semi-colon. Compiler directives are not bound by modules or by files. The effect of a compiler directive starts from the place where it appears in the source code, and continues through all files processed subsequently, to the point where the directive is superseded, or the end of the last file to be processed.

`celldefine and `endcelldefine flag the module(s) between the two directives as a library cell.

`default_nettype changes the default net data type for implicit net declarations. By default, the implicit net data type is wire.

`define defines a text macro. `undef cancels a macro definition. The text will be substituted in place of the macro_name where ever the macro name is used. The macro_name must also be preceded by the grave accent each time the macro name is used. Macros can be used to improve the readability and maintainability of the Verilog code.

`ifdef, `ifndef, `elsif, `else and `endif conditionally compiles Verilog code, depending on whether or not a specified macro is defined. Any code that is not compiled must still be valid Verilog code.

`include includes the contents of another Verilog source file.

`reset_all resets all active compiler directives that have a default back to the default. Directives that have no default are not affected.

`timescale specifies the simulation time unit and precision for delays. The unit is the amount of time a delay of 1 represents. The unit must be 1, 10 or 100.Base is the time base and must be: s, ms, us, ns, ps or fs. All delays are rounded to the nearest precision. The precision must be less than or equal to the unit.

`line can be used to specify the original source code line number and filename. This allows the location in an original file to be maintained if another process modifies the source. The level indicates whether an include file has been entered (1), an include file is exited (2), or neither has been done (0).

Example:

`define CLK_PERIOD 20
always #(`CLK_PERIOD/2) Clk = ~Clk;
`ifdef RTL
  wire Q = A & B;
`else
  and #1 (Q, A, B);
`endif
`include "/common/definitions.v"
`timescale 1 ns / 10 ps