Circuits--Building--Counter--1~2

1. counter

module top_module (
    input clk,
    input reset,
    output [9:0] q
);
    reg[9:0] qt = 10'd0;
    always @(posedge clk ) begin
        if(reset)
            qt <= 10'd0;
        else if (qt == 999) begin
            qt <= 10'd0;
        end
        else 
            begin
                qt = qt + 1;
            end
           
    end

    assign q = qt;


    
endmodule

2. 4-bit shift

module top_module (
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output [3:0] q);
    
    reg[3:0] qt;
    
    always@(posedge clk)
        begin
            if(shift_ena)
                qt <= {qt[2:0],data};
            else if(count_ena)
                begin
                    if(qt == 4'd0)
                        qt <= 4'd15;
                    else
                        qt <= qt - 1'b1;
                end
        end
    
    assign q = qt;

endmodule