深度为16，位宽8bit的单端口SRAM——学习记录

 

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【Verilog HDL 训练】第 13 天（存储器、SRAM）-云社区-华为云

 

 module sram #(
      parameter ADDR_BITS=4
      )(
      input clk,
      input [ 7:0] addr,
      input [ 7:0] din,
      input ce,
      input we,
      output reg [ 7:0] dout
      );
      localparam MEM_DEPTH= 1<<ADDR_BITS;
      reg [7:0] mem[MEM_DEPTH-1:0];
      // synopsys_translate_off
      integer i;
      initial begin
      for(i=0; i<MEM_DEPTH;i=i+1) begin
      mem[i] = 8'h00;
      end
      end
      // synopsys_translate_on
      always @(posedge clk) begin
      if(ce & we) begin
      mem[addr] <= din;
      end
      end
      always @(posedge clk) begin
      if(ce && (!we)) begin
      dout <= mem[addr];
      end
      end
      endmodule

`timescale 1ns / 1ps
      //
      // Company: 
      // Create Date: 2019/05/16 21:04:57
      // Design Name: 
      // Module Name: SRAM_tb
      //
      module sram_tb(
      );
     	reg [7 : 0] addr;
     	reg [7 : 0]data_in;
     	reg clk;
     	reg we;
     	reg ce;
     	wire [7 : 0] data_out;
     	integer i;
     	//clock generation
     	initial begin
     		clk = 0;
     		forever
       #4 clk = ~clk;
     	end
     	initial begin
     		ce = 1'b0;
     		we = 1'b0;
     		addr = 4'd0;
     		data_in = 8'h00;
       #20
     		@(negedge clk)//read
     		ce = 1'b1;
     		for (i = 0; i<16; i=i+1) begin
     			@(negedge clk)
      addr = i;
     		end
     		@(negedge clk)//write
     			we = 1'b1;
     		for (i = 0; i<16; i=i+1) begin
     			@(negedge clk) begin
      addr = i;
      data_in = data_in + 'h01;
     			end
     		end
     		@(negedge clk)//read
     			we = 1'b0;
     		for (i = 0; i<16; i=i+1) begin
     			@(posedge clk)
      addr = i;
     		end
     		@(negedge clk)
     			ce = 1'b0;
     		 //#100 $finish;
       #100 $stop;
     	end
     	sram #( .ADDR_BITS(4) ) u_sram(
     	.clk(clk),
     	.ce(ce),
     	.we(we),
     	.addr(addr),
     	.din(data_in),
     	.dout(data_out)
     	);
      endmodule