Circuits--Sequential--Counters

1.Four-bit binary counter

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output [3:0] q);
 
    always@(posedge clk)
        begin
            if(reset)
                q<=0;
            else
                begin
                   q<=q+1'b1; 
                end
        end
    
endmodule

2.Decade counter

module top_module (
    input clk,
    input reset,        // Synchronous active-high reset
    output [3:0] q);
 
    always@(posedge clk)
        begin
            if(reset)
                q<=0;
            else 
                begin
                if(q<4'b1010)
                    q<=q+1'b1;
                if(q==4'b1001)
                    q<=0;
                end
        end
    
endmodule

3.Decade counter  again

module top_module (
    input clk,
    input reset,
    output [3:0] q);
    
    always@(posedge clk)
        begin
            if(reset)
                q<=1;
            else
                begin
                    if(q<10)
                        q<=q+1;
                    else
                        q<=1;
                end
                
        end
 
endmodule

4.Slow decade counter

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);
 
    always@(posedge clk)
        begin
            if(reset)
                q<=0;
            else
                begin
                    if(slowena==0)
                        q<=q;
                    else
                        begin
                        if(q<10)
                            q<=q+1;
                        if(q==9)
                            q<=0;
                        end
                end
        end
    
endmodule

5.Counter 1-12

module top_module (
    input clk,
    input reset,
    input enable,
    output [3:0] Q,
    output c_enable,
    output c_load,
    output [3:0] c_d
); //
 
    assign c_enable=enable;
    assign c_load = (reset|((enable==1)&(Q==4'd12)));  //将counter置为1
    assign c_d = c_load ? 4'd1 : 4'd0;
    count4 the_counter (clk, c_enable, c_load, c_d ,Q);
   
endmodule

6.Counter 1000

module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); //
 
    wire [3:0] one;
    wire [3:0] ten;
    wire [3:0] hun;
    
    assign c_enable = {(one==9)&(ten==9),(one==9),1'b1};
    assign OneHertz = {(one==9)&(ten==9)&(hun==9)};
    bcdcount counter0 (clk, reset, c_enable[0],one);
    bcdcount counter1 (clk, reset, c_enable[1],ten);
    bcdcount counter2 (clk, reset, c_enable[2],hun);
endmodule

7. 4-digit decimal counter

module top_module (
    input           clk,
    input           reset,
    output [3:1]    ena,
    output [15:0]   q 
);

    reg [3:0] one;
    reg [3:0] ten;
    reg [3:0] hun;
    reg [3:0] thou;

    always @(posedge clk) begin
        if (reset) begin
            one <= 4'b0;
        end

        else if(one == 4'd9) begin
            one <= 4'b0;
        end  
        else begin
            one <= one + 4'd1;
        end
        
    end

    always @(posedge clk) begin
        if (reset) begin
            ten <= 4'b0;
        end
       
        else if ((one == 4'd9) & (ten == 4'd9)) begin
            ten <= 4'b0;
        end
        
        else if (one == 4'd9) begin
            ten <= ten + 4'd1;
        end
    end

    always @(posedge clk) begin
        if (reset) begin
            hun <= 4'b0;
        end
       
        else if ((one == 4'd9) & (ten == 4'd9) & (hun == 4'd9)) begin
            hun <= 4'b0;
        end
        
        else if ((one == 4'd9) & (ten  == 4'd9)) begin
            hun <= hun + 4'd1;
        end
    end
    
    always @(posedge clk) begin
        if (reset) begin
            thou <= 4'b0;
        end
       
        else if ((one == 4'd9) & (ten == 4'd9) & (hun == 4'd9) & (thou == 4'd9)) begin
            thou <= 4'b0;
        end
        
        else if ((one == 4'd9) & (ten  == 4'd9) & (hun == 4'd9)) begin
            thou <= thou + 4'd1;
        end
    end

    assign q = {thou,hun,ten,one};
    assign ena[1] = (one == 4'd9) ? 1'b1 : 1'b0;
    assign ena[2] =((ten == 4'd9) & (one == 4'd9)) ? 1'b1 : 1'b0;
    assign ena[3] = ((hun == 4'd9) & (ten == 4'd9) & (one == 4'd9)) ? 1'b1 : 1'b0;

endmodule

8.12-hour clock

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
	
    cnt12 cnt_h(clk, reset, ena&&ss==8'h59&&mm==8'h59, pm, hh);
    cnt60 cnt_m(clk, reset, ena&&ss==8'h59, mm);
    cnt60 cnt_s(clk, reset, ena, ss);
endmodule
 
// 1-12计数器module
module cnt12(input clk, 
             input reset, 
             input ena, 
             output pm, 
             output reg[7:0] q
             );

    always @(posedge clk) begin
        if(reset) begin
            q <= 8'h12;  	//重置为12点
            pm <= 0;	    //重置为am
        end
        else if(ena) begin
            if(q == 8'h12)  //到12点就重置为1点
                q <= 8'h01;
            else if(q[3:0] == 9) begin  
           		q[3:0] <= 0;   
            	q[7:4] <= q[7:4] + 1;
            end
            else
                q[3:0] <= q[3:0] + 1;
        end
        pm <= (q == 8'h11) && ena ? ~pm : pm;  
       
    end
endmodule

// 0-59计数器module
module cnt60(input clk,
             input reset, 
             input ena, 
             output reg[7:0] q
);

    always @(posedge clk) begin
        if(reset)
            q <= 0;
        else if(ena) begin
            if(q[3:0] == 9) begin
            	q[3:0] <= 0;
                if(q[7:4] == 5)    //q=8'h59复位
                    q[7:4] <= 0;
                else
                    q[7:4] <= q[7:4] + 1;
            end
            else
            	q[3:0] <= q[3:0] + 1;
        end
    end
endmodule