Verilog---Procedures

最新推荐文章于 2024-07-17 18:38:35 发布

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最新推荐文章于 2024-07-17 18:38:35 发布

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分类专栏： HDLBits 文章标签：笔记 fpga开发

本文链接：https://blog.csdn.net/pmlcreating/article/details/137131469

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这篇文章详细介绍了Verilog语言中Alwaysblocks的不同用法，包括无时钟的组合逻辑、带时钟的同步组合及异步组合、if语句、latch的使用、case和priorityencoder结构，以及如何避免不必要的latches。

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1.Always blocks(combinational)

module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);

    assign out_assign=a&b;
    always@(*)
        begin
           out_alwaysblock=a&b; 
        end
    
endmodule

2.Always blocks(clocked)

module top_module(
    input clk,
    input a,
    input b,
    output wire out_assign,
    output reg out_always_comb,
    output reg out_always_ff   );
    
    assign out_assign=a^b;
    always@(*)
        begin
           out_always_comb=a^b;
        end
    
    always@(posedge clk)
        
        out_always_ff<=a^b;
        

endmodule

3.if statement

module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   ); 
    
    assign out_assign = (sel_b1 & sel_b2) ? b : a;
    always@(*)
        begin
            if(sel_b2&sel_b1)
                begin
                out_always = b;
                end
            else 
                begin
                  out_always = a;
                end
        end
    
    
    

endmodule

4.if statement latches

module top_module (
    input      cpu_overheated,
    output reg shut_off_computer,
    input      arrived,
    input      gas_tank_empty,
    output reg keep_driving  ); //

    always @(*) begin
        if (cpu_overheated)
           shut_off_computer = 1;
        else shut_off_computer = 0;
    end

    always @(*) begin
        if (~arrived)
           keep_driving = ~gas_tank_empty;
        else keep_driving = 0;
    end

endmodule

5.Case statement

module top_module ( 
    input [2:0] sel, 
    input [3:0] data0,
    input [3:0] data1,
    input [3:0] data2,
    input [3:0] data3,
    input [3:0] data4,
    input [3:0] data5,
    output reg [3:0] out   );//

    always@(*) begin  // This is a combinational circuit
        case(sel)
            3'b000: out=data0;
            3'b001: out=data1;
            3'b010: out=data2;
            3'b011: out=data3;
            3'b100: out=data4;
            3'b101: out=data5;
            default: out=3'b000;
        endcase
    end

endmodule

6.Priority encoder

module top_module (
    input [3:0] in,
    output reg [1:0] pos  );
   always@(*)
        begin
    case(in)
        4'b0000: pos=3'd0;
        4'b0001: pos=3'd0;
        4'b0010: pos=3'd1;
        4'b0011: pos=3'd0;
        4'b0100: pos=3'd2;
        4'b0101: pos=3'd0;
        4'b0110: pos=3'd1;
        4'b0111: pos=3'd0;
        4'b1000: pos=3'd3;
        4'b1001: pos=3'd0;
        4'b1010: pos=3'd1;
        4'b1011: pos=3'd0;
        4'b1100: pos=3'd2;
        4'b1101: pos=3'd0;
        4'b1110: pos=3'd1;
        4'b1111: pos=3'd0;
        default: pos=3'd0;
    endcase
            end
    

endmodule

7.Priority encoder with casez

module top_module (
    input [7:0] in,
    output reg [2:0] pos );
    
    always@(*)
        begin
            casez(in[7:0])
               // 8'bzzzz_zzzz: pos=3'd0;
                8'bzzzz_zzz1: pos=3'd0;
                8'bzzzz_zz1z: pos=3'd1;
                8'bzzzz_z1zz: pos=3'd2;
                8'bzzzz_1zzz: pos=3'd3;
                8'bzzz1_zzzz: pos=3'd4;
                8'bzz1z_zzzz: pos=3'd5;
                8'bz1zz_zzzz: pos=3'd6;
                8'b1zzz_zzzz: pos=3'd7;
                default: pos=3'd0;
            endcase
        end

endmodule

8.Avoiding latches

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  ); 
    
    always@(*)
        begin
           up=1'b0; down=1'b0; left=1'b0;right=1'b0;
            case(scancode)
                16'he06b: left=1'b1;
                16'he072: down=1'b1;
                16'he074: right=1'b1;
                16'he075: up=1'b1;
                
            endcase
        end

endmodule