GD32450i-EVAL学习笔记 4 - SPI Master

目录

1. GPIO初始化

2. 使能RCU

3. 初始化SPI端口

4. 读写

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GD32F450一共支持6组SPI，其中仅SPI1和SPI2支持全双工模式的主从操作，仅SPI5支持QSPI主操作。

SPI1和SPI2的时钟源是APB1，SPI0、SPI3、SPI4和SPI5的时钟源是APB2。因为APB1和APB2的最大频率为50M和100M，所以，SPI1和SPI2的最大频率是25M，而其他SPI的最大频率可以到50M。

1. GPIO初始化

以SPI5为例

rcu_periph_clock_enable(RCU_GPIOG);
//G13: SCK, G12: MISO, G14: MOSI, G10: IO2, G11: IO3
gpio_af_set(GPIOG, GPIO_AF_5, GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14);
gpio_mode_set(GPIOG, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14);
gpio_output_options_set(GPIOG, GPIO_OTYPE_PP, GPIO_OSPEED_25MHZ, GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14);

2. 使能RCU

rcu_periph_clock_enable(RCU_SPI5);

3. 初始化SPI端口

void spimCfg(uint32_t SPIx, uint16_t prescaler)
{
    spi_parameter_struct spi_init_struct;
    spi_init_struct.trans_mode           = SPI_TRANSMODE_FULLDUPLEX;
    spi_init_struct.device_mode          = SPI_MASTER;
    spi_init_struct.frame_size           = SPI_FRAMESIZE_8BIT;
    spi_init_struct.clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE;
    spi_init_struct.nss                  = SPI_NSS_SOFT;
    spi_init_struct.prescale             = prescaler;
    spi_init_struct.endian               = SPI_ENDIAN_MSB;
    spi_init(SPIx, &spi_init_struct);
    
    /* set crc polynomial */
    spi_crc_polynomial_set(SPIx, 7);

    /* enable */
    spi_enable(SPIx);
}

4. 读写

void spimTransferBytes(uint8_t port, uint8_t* wrBuf, uint8_t* rdBuf, uint16_t len)
{
    uint16_t i;
    uint32_t SPIx;
    if(len == 0 || port >= HW_SPI_MAX)
        return;
    SPIx = spimGroup[port];
    while(0 == (SPI_STAT(SPIx) & SPI_FLAG_TBE));
    for(i = 0; i < len; i++)
    {
        SPI_DATA(SPIx) = (wrBuf != NULL) ? wrBuf[i] : 0xff;
        // Wait to receive a byte  
        while((SPI_STAT(SPIx) & SPI_FLAG_RBNE) == 0);
        if(rdBuf != NULL)
            rdBuf[i] = (uint8_t)SPI_DATA(SPIx);
        else
            SPI_DATA(SPIx);
    }
}