Chisel 入门

each creation of a component adds hardware;
each assignment statement generates gates and/or flip flops.

When Chisel executes your code it runs as a Scala program, and by executing the Chisel statements, it collects the hardware components and connects those nodes.

Project Tree

Source tree of a typical chisel project:

project (contains build.sbt, Makefile, README, LICENCE)
	|===src(contains all sourcecode)
			|==|main(hardware source codes)
			|====|scala(Chisel inherits from Scala)
			|======|package(Scala inherits from Java's packages)
			|=========|subpackage
			|==|test(testers)
			|====|scala
			|======|package
	|==target(contains the class files and other generated files)
	|==generated(for generated Verilog files)