RISC-V - 16, 32, 64

RISC-V allows mixing 16-bit, 32-bit, 48-bit, 64-bit instructions, and beyond!

RV32I defines a 32-bit computer architecture, where registers are 32-bits wide. Its instructions are all 32-bits wide. For example, it has lw to load a 32-bit word into a register, and, add to add two registers and target a third.

RV64I defines a 64-bit computer architecture, where registers are 64-bits wide (hence RV64) — its instructions are also 32-bits wide. The RV32 instructions still work, and there are some additional instructions to accommodate both 32-bit and 64-bit operations. For example, lw still loads a 32-bit word (though now sign extends to fill the 64-bit register), and so a new instruction is used ld to load a 64-bit word. add still adds two registers and targets a third, but this same add is now doing 64-bit addition instead of 32-bit addition, since the registers are 64-bits in RV64. A new instruction addw does 32-bit addition, in case that was all you wanted.

RVC is an extension that can be added to either RV32I or RV64I. When present it allows for 16-bit instructions, and, its design is such that a 16-bit instruction expands 1:1 into a 32-bit wide instruction — because of this there are no changes to the register architecture (of either the RV32 or RV64 that RVC was added to), and in some sense, there’s nothing new they can do that isn’t already in the 32-bit wide instruction set. We should think of it more a space saving technique rather than some new capabilities.

The base architecture (that is, without RVC) allows for branches to 16 bit boundaries. The PC and return addresses and all branching instructions support any even byte value, so when RVC is added to something, the other instructions don’t change. This artifact also supports 48-bit and 64-bit instructions, though there are no extensions defined for those sizes as yet.