VHDL中with select when语法

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX41A IS
PORT(a,b,c,d,s0,s1:IN STD_LOGIC;y:OUT STD_LOGIC);
END ENTITY MUX41A;
ARCHITECTURE BHV OF MUX41A IS
SIGNAL S:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
S<=s1&s0; //拼接
WITH S SELECT
y<=a WHEN "00", //S的值
   b WHEN "01",
   c WHEN "10",
   d WHEN "11";
END BHV;