VHDL——4选1多路选择器

1.条件信号赋值语句

library ieee;
use ieee.std_logic_1164.all;

entity mux4 is
    port(i0,i1,i2,i3,a,b : in std_logic;
	      q : out std_logic);
end mux4;

architecture rtl of mux4 is
  signal sel : std_logic_vector(1 downto 0);
begin
    sel <= b&a;
	 q <= i0 when sel = "00" else            --条件赋值语句，给q赋值
	      i1 when sel = "01" else
		  i2 when sel = "10" else
		  i3 when sel = "11" ;
end rtl;

2.选择信号赋值语句

library ieee;
use ieee.std_logic_1164.all;

entity mux4 is
    port(i0,i1,i2,i3,a,b : in std_logic;
	      q : out std_logic);
end mux4;

architecture rtl of mux4 is
  signal sel : std_logic_vector(1 downto 0);
begin
  sel <= a&b;
  with sel select            --选择信号赋值语句
    q <= i0 when "00",
	     i1 when "01",
	     i2 when "10",
	     i3 when "11",
	     'X' when others;
end rtl;