学习记录：VerilogHDL

There are three types of assignments in Verilog:
1：持续赋值语句（assign x = y;）不可以在过程语句中使用（“always block”）。
2：过程阻塞赋值只能在过程模块中使用。
3： 过程非阻塞赋值只能在过程模块中使用。

1：Continuous assignments (assign x = y;). Can only be used when not inside a procedure (“always block”).
2：Procedural blocking assignment: (x = y;). Can only be used inside a procedure.
3：Procedural non-blocking assignment: (x <= y;). Can only be used inside a procedure.

在组合逻辑的always语句块里面使用阻塞赋值，在时钟驱动的always语句块中使用非阻塞赋值。
In a combinational always block, use blocking assignments. In a clocked always block, use non-blocking assignments.

如果不遵守上面的规则，将会导致难于察觉的错误，以及仿真和真实生成电路的差异。
A full understanding of why is not particularly useful for hardware design and requires a good understanding of how Verilog simulators keep track of events. Not following this rule results in extremely hard to find errors that are both non-deterministic and differ between simulation and synthesized hardware.