【verilog HDL】

Verilog HDL刷题记录1：Module addsub

An adder-subtractor can be built from an adder by optionally negating one of the inputs, which is equivalent to inverting the input then adding 1. The net result is a circuit that can do two operations: (a + b + 0) and (a + ~b + 1). See Wikipedia if you want a more detailed explanation of how this circuit works.
Build the adder-subtractor below.
You are provided with a 16-bit adder module, which you need to instantiate twice:
module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );
Use a 32-bit wide XOR gate to invert the b input whenever sub is 1. (This can also be viewed as b[31:0] XORed with sub replicated 32 times. See replication operator.). Also connect the sub input to the carry-in of the adder.
注： 这里的意思是，根据输入sub的值来决定是否对b进行异或操作。

module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);
    wire carry;
    wire [31:0] bx = sub?b^{32{sub}}:b;
    add16 add16_ins1(a[15:0],bx[15:0],sub,sum[15:0],carry);
    add16 add16_ins2(a[31:16],bx[31:16],carry,sum[31:16]);
endmodule