Exams/ece241 2013 q8 HDLbits刷题

Exams/ece241 2013 q8
Implement a Mealy-type finite state machine that recognizes the sequence “101” on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the “101” sequence is detected. Your FSM should also have an active-low asynchronous reset. You may only have 3 states in your state machine. Your FSM should recognize overlapping sequences.
设计状态米勒状态机，状态图如下。

直接上代码:

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z ); 
    parameter start = 0,mid = 1,ends = 2;
    reg [2:0] state,next_state;
    
    always@(*)begin
        case(state)
        	start:next_state = x?mid:start;
            mid:next_state = x?mid:ends;
            ends:next_state = x?mid:start;
        endcase
    end
    
    always@(posedge clk or negedge aresetn)begin
        if(!aresetn)
            state <= start;
        else
            state <= next_state;
    end
    
    assign z = ((state == start) || (state == mid))?0:x;
   
endmodule

最后的判断可能不够直接，可以改为如下的形式。

   always@(*)begin
        if(state == ends && x == 1)
            z = 1;
        else
            z = 0;    
    end

首先可以看到米勒是由当时的状态和输入决定的，其次米勒状态机会提前一个节拍进行判断，就像控制系统里的预测控制一样。相当于说在收到101的第二个1的一开始就要把标志进行置位。

Exams/ece241 2014 q5b
The following diagram is a Mealy machine implementation of the 2’s complementer. Implement using one-hot encoding.
题目意思是这是两位的补码器，是用米勒状态机进行设计。
下面是代码：

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    parameter normal =0,reverse = 1;
    reg [2:0] state ,next_state;
    
    always@(*)begin
        case(state)
        	normal:next_state = x?reverse:normal;
            reverse:next_state = reverse;
            default:next_state = reverse;
        endcase  
    end
    
    always@(posedge clk,posedge areset)begin
        if(areset)
            state <= normal;
        else
            state <= next_state;
    end
    assign z = (state == reverse && x==1'b0) || (state == normal && x == 1'b1);  
endmodule

Exams/ece241 2014 q5a
You are to design a one-input one-output serial 2’s complementer Moore state machine. The input (x) is a series of bits (one per clock cycle) beginning with the least-significant bit of the number, and the output (Z) is the 2’s complement of the input. The machine will accept input numbers of arbitrary length. The circuit requires an asynchronous reset. The conversion begins when Reset is released and stops when Reset is asserted.
这道题建议先去写Exams/ece241 2014 q5b，对于题目的理解有比较大的帮助。
这个题目说的很清楚，是设计一个摩尔状态机，也就是输出只和状态有关，和输入无关。

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    parameter idle = 0,start = 1,neg = 2,pos =3;
    reg [1:0] state,next_state;
    
    always@(*)begin
        case(state)
            idle:next_state = x?start:idle;
            start:next_state = x?pos:neg;
            pos:next_state = x?pos:neg;
            neg:next_state = x?pos:neg;
        endcase
    end
    
    always@(posedge clk or posedge areset)begin
        if(areset)
            state <= idle;
        else
            state <= next_state;
    end
    
    assign z = (state == start) || (state == neg);
endmodule

到这里关于补码的内容已经结束，希望你我都有收获，再会。