Xilinx的FPGA在使用DCM时的问题解决方案

在使用Xilinx的FPGA开发板时，在设计时内部需要使用不同的时钟频率，可能会需要一个甚至多个DCM把所需要的时钟频率倍频或者是分频出来，在编译、综合、映射、布局布线的过程中会出现下列问题（ERROR）： 
ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM 
   site pair.  The clock component <u1/u0/DCM_SP_INST> is placed at site <DCM_X0Y1>.  The clock IO/DCM site can be 
   paired if they are placed/locked in the same quadrant.  The IO component <clk> is placed at site <P32>.  This will 
   not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable 
   for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a 
   WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to 
   very poor timing results. It is recommended that this error