Clock Buffer Basics

Clocksare the basic building blocks for all electronics today. For every datatransition in a synchronous digital system, there is a clock that controls aregister. Most systems use Crystals, Frequency Timing Generators (FTGs), orinexpensive ceramic resonators to generate precision clocks for theirsynchronous systems. Additionally, clock buffers are used to create multiplecopies, multiply and divide clock frequencies, and even move clock edgesforwards or backward in time. Many clock-buffering solutions have been createdover the past few years to address the many challenges required by today’shigh-speed logic systems. Some of these challenges include: High operating andoutput frequencies, propagation delays from input to output, output to outputskew between pins, cycle-to cycle and long-term jitter, spread spectrum, outputdrive strength, I/O voltage standards, and redundancy. Because clocks are thefastest signals in a system and are usually under the heaviest loads, specialconsideration must be given when creating clocking trees. In this chapter, weoutline the basic functions of non-PLL and PLL-based buffers and show how thesedevices can be used to address the high-speed logic design challenges.

Intoday’s typical synchronous designs, multiple clock signals are often needed todrive a variety of components. To create the required number of copies, a clocktree is constructed. The tree begins with a clock source such as an oscillatoror an external signal and drives one or more buffers. The number of buffers istypically dependent on the number and placement of the target devices. Figure2.1 illustrates the concept of the clock tree.

Inyears past, generic logic components were used as clock buffers. These wereadequate at the time, but they did little to maintain the signal integrity ofthe clock. In fact, they actually were a detriment to the circuit. As clocktrees increased in speed and timing margins reduced, propagation delay andoutput skew became increasingly important. In the next several sections, wediscuss the older devices and why they are inadequate to meet the needs oftoday’s designs. The definitions of the common terms associated with modernbuffers follow. Finally, we address the attributes of the modern clock bufferwith and without a PLL. The FTG that is often used as a clock source is aspecial type of PLL clock buffer. A discussion of these devices can be found inChapter 12.

Figure 2.1 Typical ClockTree

EarlyBuffers: A clock buffer is a device in which the output waveform follows theinput waveform. The input signal propagates through the device and is re-drivenby the output buffers. Hence, such devices have a propagation delay associatedwith them. In addition, due to differences between the propagation delaythrough the device on each input-output path, skew will exist between theoutputs. An example of a non-PLL based clock buffer is the 74F244 that is available from severalmanufacturers. These devices have been available for many years and weresuitable for designs where frequencies were below 20 MHZ. Designers would bringin a clock and fan it out to multiple synchronous devices on a circuit card.With these slow frequencies and associated rise times, designers had suitablemargins with which to meet setup and hold times for their synchronousinterfaces. However, these buffers are not optimal for today’s high-speedclocking requirements. The 74F244suffers from a long propagation delay (3 to 5 ns) and long output-to-outputskew delays. Non- PLL based clock buffers have improved in recent years and usemore advanced I/O design techniques to improve the output-to-output skew. Asthe clock period gets shorter, the uncertainty or skew in the clockdistribution system becomes more of a factor. Since clocks are used to drivethe processors and to synchronize the transfer of data between systemcomponents, the clock distribution system is an essential part of the systemdesign. A clock distribution system design that does not take skew intoconsideration may result in a system with degraded performance and reliability.

ClockSkew: Skew is the variation in the arrival time of two signals specified tooccur at the same time. Skew is composed of the output skew of the drivingdevice and variation in the board delays caused by the layout variation of theboard traces. Since the clock signal drives many components of the system, andsince all of these components should receive their clock signal at preciselythe same time in order to be synchronized, any variation in the arrival of theclock signal at its destination will directly impact system performance. Skewdirectly affects system margins by altering the arrival of a clock edge.Because elements in a synchronized system require clock signals to arrive atthe same time, clock skew reduces the cycle time within which information canbe passed from one device to the next. As system speeds increase, clock skewbecomes an increasingly large portion of the total cycle time. When cycle timeswere 50 ns, clock skew was rarely a design priority. Even if skew was 20% ofthe cycle time, it presented no problem. As cycle times dropped to 15 ns andless, clock skew requires an ever-increasing amount of design resource. Nowtypically, these high-speed systems can have only 10% of their timing budgetdedicated to clock skew, so obviously, it must be reduced.

Thereare two types of clock skew that affect system performance. The clock drivercauses intrinsic skew and the printed circuit board (PCB) layout and design isreferred to as extrinsic skew. Extrinsic skew and layout procedures for clocktrees will be discussed later in this book. The variation of time due to skewis defined by the following equation:

tSKEW _INTRINSIC = Device Induced Skew

tSKEW_EXTRINSIC = PCB + Layout + Operating Environment Induced Skew

tSKEW = t SKEW_INTRINSIC + t SKEW_EXTRINSIC

Intrinsicclock skew is the amount of skew caused by the clock driver or buffer byitself. Board layout or any other design issues, except for the specificationstated on the clock driver data sheet do not cause intrinsic skew.

OutputSkew: Output skew (TSK) is also referred to as pin-to-pin skew. Output skew isthe difference between delays of any two outputs on the same device atidentical transitions. Joint Electronic Device Engineering Council (JEDEC)defines output skew as the skew between specified outputs of a single devicewith all driving inputs connected together and the outputs switching in thesame direction while driving identical specified loads. Figures 2.2 and 2.3show a clock buffer with common input CIN driving outputs Co1_1 through Co1_n.The absolute maximum difference between the rising edges of the outputs will bespecified as output skew. Typical outp