verlog产生随机数

verlog产生随机数

module ram(clk,load,rst_n,seed,ran_num);

input clk,rst_n,load;
output reg [7:0] ran_num;
input [7:0]seed;
integer i;
always@(posedge clk or negedge rst_n)
if(!rst_n)
	ran_num<=8'b0;
else if(load)
	ran_num<=seed;
else
	begin
		for(i=1;i<8;i=i+1)
			ran_num[i]<=ran_num[i-1];
		ran_num[0]<=ran_num[7]^(ran_num[2]^(ran_num[3]^ran_num[4]));
	end


endmodule

seed为输入数，load为将输入载入使能
以下为测试文件

`timescale 1ns/1ns
module ram_tb;
	reg clk,rst_n,load;
	wire [7:0] ran_num;
	reg [7:0]seed;
	
	
	ram ram_inst(
				.clk(clk),
				.rst_n(rst_n),
				.load(load),
				.seed(seed),
				.ran_num(ran_num));			
				
	initial 
	begin
		clk=0;rst_n=0;
		#10 rst_n=1;
		#10 seed={$random}%125;
		#10 load=1;
		#10 load=0;		
		#1000;	
	end
	
	initial
	$monitor("time %d\ran_num %b",$time,ran_num);
	
always #10 clk=~clk;	
endmodule