一、实验目的
(1)掌握利用有限状态机实现一般时序逻辑分析的方法;
(2)掌握用Verilog编写可综合的有限状态机的标准模板;
(3)掌握用Verilog编写状态机模块的测试文件的一般方法。
二、实验原理
在数字电路中已经学习过通过建立有限状态机来进行数字逻辑的设计,而在Verilog HDL硬件描述语言中,这种设计方法得到进一步的发展。通过Verilog HDL提供的语句,可以直观地设计出更为复杂的时序逻辑的电路。关于有限状态机的设计方法在教材中已经作了较为详细的阐述,在此就不赘述了。
下例是一个简单的状态机设计,功能是检测一个5位二进制序列“10010”。考虑到序列重叠的可能,有限状态机共提供8个状态(包括初始状态IDLE)。
模块源代码:
//-------------- seqdet.v --------------
module seqdet(x,z,clk,rst,state);
input x,clk,rst;
output z;
output [2:0] state;
reg [2:0] state;
wire z;
parameter IDLE = 'd0, A = 'd1, B = 'd2,
C = 'd3, D = 'd4,
E = 'd5, F = 'd6,
G = 'd7;
assign z = (state == E && x == 0)?1:0;
always @(posedge clk)
if(!rst)
begin
state <= IDLE;
end
else
casex(state)
IDLE: if(x == 1)
begin
state <= A;
end
A: if(x == 0)
begin
state <= B;
end
B: if(x == 0)
begin
state <= C;
end
else
begin
state <= F;
end
C: if(x == 1)
begin
state <= D;
end
else
begin
state <= G;
end
D: if(x == 0)
begin
state <= E;
end
else
begin
state <= A;
end
E: if(x == 0)
begin
state <= C;
end
else
begin
state <= A;
end
F: if(x == 1)
begin
state <= A;
end
else
begin
state <= B;
end
G : if(x == 1)
begin
state <= F;
end
default: state = IDLE;
endcase
endmodule
测试模块源代码:
//-------------- seqdet_Top.v --------------
`timescale 1ns/1ns
`include "./seqdet.v"
module seqdet_Top;
reg clk,rst;
reg [23:0] data;
wire [2:0] state;
wire x,z;
assign x = data[23];
always #10 clk = ~clk;
always @(posedge clk)
data = {data[22:0],data[23]};
initial
begin
clk = 0;
rst = 1;
#2 rst = 0;
#30 rst = 1;
data = 'b1100_1001_0000_1001_0100;
#500 $stop;
end
seqdet m(.x(x),.z(z),.clk(clk),.rst(rst),.state(state));
endmodule
状态机设计的仿真波形如下图所示:
三、实验要求及实验内容
(1)实验内容:
设计一个串行数据检测器。要求是:连续4个或4个以上为1时输出为1,其他输入情况下为0。编写测试模块对设计的模块进行各种层次的仿真,并观察波形,编写实验报告。
(2)实验代码:
模块源代码:
//-------------- four_one.v --------------
module four_one(x,z,clk,rst,state);
input x,clk,rst;
output z;
output [2:0] state;
reg [2:0] state;
wire z;
parameter IDLE = 'd0, A = 'd1, B = 'd2, C = 'd3, D = 'd4;
assign z = (state == D)?1:0;
always @(posedge clk)
if(!rst)
begin
state <= IDLE;
end
else
casex(state)
IDLE: if(x == 1)
begin
state <= A;
end
else
begin
state <= IDLE;
end
A: if(x==1)
begin
state<=B;
end
else
begin
state <= IDLE;
end
B: if(x==1)
begin
state<=C;
end
else
begin
state <= IDLE;
end
C: if(x==1)
begin
state<=D;
end
else
begin
state <= IDLE;
end
D: if(x==1)
begin
state<=D;
end
else
begin
state <= IDLE;
end
default: state = IDLE;
endcase
endmodule
测试模块源代码:
//-------------- four_one_Top.v --------------
`timescale 1ns/1ns
`include "./four_one.v"
module four_one_Top;
reg clk,rst;
reg [23:0] data;
wire [2:0] state;
wire x,z;
assign x = data[23];
always #10 clk = ~clk;
always @(posedge clk)
data = {data[22:0],data[23]};
initial
begin
clk = 0;
rst = 1;
#2 rst = 0;
#30 rst = 1;
data = 'b1100_1001_0111_1101_0100_1111;
end
four_one m(.x(x),.z(z),.clk(clk),.rst(rst),.state(state));
endmodule
四、实验结果