Verilog交通灯设计+FPGA(DE2+ESP2C35F672C6）

⌘⌘最详细步骤⌘⌘

希望照片里面的每一个步骤，都要认认真真的看一遍。

1.新建工程文件

2.打开Quartus II软件

3.新建工程

点击Next

4.新建代码文件

有三个代码文件
TOP.V
SEGTOP.V
SEGBOT.V

TOP.V代码

`timescale 1ns/1ps
module TOP(clk,rst,night,R,G,Y,T,close);
input clk,rst,night;
output reg R,G,Y,close;
output reg[5:0] T;
reg[5:0] T1;
reg[5:0] T2;
reg[2:0] state;
reg[30:0] cnt;
reg[30:0] cnt_1;
always@(posedge clk or negedge rst) //clk的上升沿触发和rst的下降触发
if(!rst)
	begin
		R<=1'b0;
		G<=1'b0;
		Y<=1'b0;
		close<=1'b1;
		cnt<=31'd0;
		cnt_1<=31'd0;
		T<=6'd0;
		T1<=6'd0;
		T2<=6'd0;
		state<=3'd0;
	end
else if(night)
	case(state)
		3'd0:
			begin
				R<=1'b0;
				G<=1'b0;
				Y<=1'b0;
				close<=1'b1;
				cnt<=31'd25000000;//0.5S
				state<=3'd1;
			end
		3'd1:
			begin
				cnt<=cnt-1'b1;
				state<=(cnt==31'd0)?3'd2:3'd1;
			end
		3'd2:
			begin
				R<=1'b0;
				G<=1'b0;
				Y<=1'b1;
				cnt<=31'd25000000;
				state<=3'd3;
			end
		3'd3:
			begin
				cnt<=cnt-1'b1;
				state<=(cnt==31'd0)?3'd0:3'd3;
			end
		default:
			state<=state;
	endcase
else
	case(state)
		3'd0:
			begin
			close<=1'b0;
			R<=1'b1;
			G<=1'b0;
			Y<=1'b0;
			cnt<=31'd1500000000;
			cnt_1<=31'd0;
			T1<=6'd30;
			T2<=6'd0;
			state<=3'd1;
		end
		3'd1:
			begin
				cnt_1<=(cnt_1==31'd50000000)?31'd0:cnt_1+1'b1;
				T2<=(cnt_1==31'd49999999)?T2+1'b1:T2;           //每隔一秒加1
				T<=T1-T2;
				cnt<=cnt-1'b1;
				state<=(cnt==31'd0)?3'd2:3'd1;
			end
		3'd2:
			begin
				R<=1'b0;
				G<=1'b1;
				Y<=1'b0;
				cnt<=31'd1500000000;
				cnt_1<=31'd0;
				T1<=6'd30;
				T2<=6'd0;
				state<=3'd3;
			end
		3'd3:
			begin
				cnt_1<=(cnt_1==31'd50000000)?31'd0:cnt_1+1'b1;
				T2<=(cnt_1==31'd49999999)?T2+1'b1:T2;
				T<=T1-T2;
				cnt<=cnt-1'b1;
				state<=(cnt==31'd0)?3'd4:3'd3;
			end
		3'd4:
			begin
				R<=1'b0;
				G<=1'b0;
				Y<=1'b1;
				cnt<=31'd150000000;
				cnt_1<=31'd0;
				T1<=6'd0;
				T2<=6'd61;//这里修改
				state<=3'd5;
			end
		3'd5:
			begin
				cnt_1<=(cnt_1==31'd50000000)?31'd0:cnt_1+1'b1;
				T2<=(cnt_1==31'd49999999)?T2+1'b1:T2;
				T<=T1-T2;
				cnt<=cnt-1'b1;
				state<=(cnt==31'd0)?3'd0:3'd5;
			end
	default:
		state<=state;
	endcase
endmodule

SEGTOP.V

/**************************************************************
Filename: SEGTOP.v
Function: 将输入的 
Author: ChunMu He
Date: 2021-4-27 12:09:06
***************************************************
*							引脚说明	
 
/*************个位数**********************************
HEX0[0] PIN_AF10  
HEX0[1] PIN_AB12  
HEX0[2] PIN_AC12  
HEX0[3] PIN_AD11 
HEX0[4] PIN_AE11   
HEX0[5] PIN_V14  
HEX0[6] PIN_V13  
/*************十位数**********************************
HEX1[0] PIN_V20  
HEX1[1] PIN_V21  
HEX1[2] PIN_W21  
HEX1[3] PIN_Y22  
HEX1[4] PIN_AA24  
HEX1[5] PIN_AA23  
HEX1[6] PIN_AB24 
*********************************************************/
`timescale 1ns/1ps
module SEGTOP (a,dr);
input[3:0]a;
output[6:0]dr;
assign  dr =  (a==4'b0000)?7'b1000000://0
			  (a==4'b0001)?7'b1111001://1
			  (a==4'b0010)?7'b0100100://2
			  (a==4'b0011)?7'b0110000://3
			  (a==4'b0100)?7'b0011001://4		  
			  (a==4'b0101)?7'b0010010://5			  
			  (a==4'b0110)?7'b0000010://6
			  (a==4'b0111)?7'b1111000://7		  
          	  (a==4'b1000)?7'b0000000://8
			  (a==4'b1001)?7'b0010000://9		  
           	  (a==4'b1010)?7'b1111111:	dr;//全灭
endmodule	

SEGBOT.V

/**************************************************************
Filename:SEGBOT.v
Function: 将输入的7位二进制数转换成2个4位的BCD码(分离十位和个位)
Author: ChunMu He
Date: 2021-4-27 12:09:06
*********************************************************/
module SEGBOT(T,close,a0,a1);
input[5:0]T;
input close;
output[3:0]a0;
output[3:0]a1;
assign a0=(close==1'b1)?4'd10:
         	 (T<6'd10)? T:
			 (T<6'd20)? T-6'd10:
			 (T<6'd30)? T-6'd20:
			 (T<6'd40)? T-6'd30:
			 (T<6'd50)? T-6'd40:
			 (T<6'd60)? T-6'd50:
			 (T<7'd70)? T-6'd60: a0;
assign a1=(close==1'b1)?4'd10:
          	 (T<6'd10)? 4'd0:
			 (T<6'd20)? 4'd1:
			 (T<6'd30)? 4'd2:
			 (T<6'd40)? 4'd3:
			 (T<6'd50)? 4'd4:
			 (T<6'd60)? 4'd5:
			 (T<7'd70)? 4'd6:a1;
endmodule

生成元器件，三个点V文件都要生，步骤看图

5.新建原理图文件

这样说明你就成功啦

6.添加引脚

已经添加好的引脚

7.进入下载程序的界面

添加最核心的驱动程序进行下载

8.工程文件下载

链接: 参考文件.
链接: 工程文件.