fsm练习

模块代码

module fsm(
	input 	wire 				sclk,
	input 	wire 				rst_n,
	
	input	wire 				A,
	output 	reg 				k1,
	output  reg 				k2
	);

parameter	IDLE	= 	4'b0001;
parameter	START	= 	4'b0010;
parameter	STOP	= 	4'b0100;
parameter	CLEAR	= 	4'b1000;

reg		[3:0]		state;	
//4'b0001  4'b0010 4'b0100 4'b1000  独热码占用寄存器逻辑多，占用组合逻辑少
//2'b00 2'b01 2'b10 2'b11           二进制编码用的寄存器数量少，但是用的组合逻辑资源较多

//第一段状态机
always @(posedge sclk or negedge rst_n)
	if(rst_n == 1'b0)
		state <= IDLE;
	else
		case(state)
				IDLE:if(A == 1'b1)
						state <= START;
			    START:if(A == 1'b0)
						state <= STOP;
				STOP:if(A == 1'b1)
						state <= CLEAR;
				CLEAR:if(A == 1'b0)
						state <= IDLE;
				default:state <= IDLE;
		endcase
always @(posedge sclk or negedge rst_n)
		if(rst_n == 1'b0)
				k1 <= 1'b0;
		else if(state == IDLE && A == 1'b1)
				k1 <= 1'b0;
		else if(state == CLEAR && A == 1'b0)
				k1 <= 1'b1;
				
always @(posedge sclk or negedge rst_n)
		if(rst_n == 1'b0)
				k2 <= 1'b0;
		else if (state == STOP && A == 1'b1)
				k2 <= 1'b1;
		else if (state == CLEAR && A == 1'b0)
				k2 <= 1'b0;
				
endmodule

仿真文件

`timescale  1ns/1ns

module fsm_tb;

reg 			sclk;
reg 			rst_n;
reg				in_a;

wire 			k1;
wire 			k2;

initial begin
		sclk  <= 0;
		rst_n <= 0;
		#100;
		rst_n <= 1;
end

initial begin
		#200
		in_data();
end

always #10 sclk <= ~sclk;

fsm	fsm_inst(
	.sclk	(sclk),		
	.rst_n 	(rst_n),
	.A		(in_a),
	.k1		(k1),
	.k2		(k2)	
);

task in_data();
		integer i;
		begin
			for(i=0;i<1024;i=i+1)
			begin
					@(posedge sclk)
					if(i<50)
						in_a <= 0;
					else if(i<200)
						in_a <= 1;
					else if(i<700)
						in_a <= 0;
					else if(i<800)
						in_a <= 1;
					else if(i<900)
						in_a <= 0;
			end
		end
endtask

endmodule