地址:HDLBits - Lemmings4
介绍:仅记录代码
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging );
parameter LEFT=2'b00,RIGHT=2'b01,DIGGING=2'b11,FALL=2'b10;
reg [1:0] current_state,next_state,state_before_fall;
reg [4:0] cnt;
reg splat_flag;
always @(posedge clk or posedge areset) begin
if (areset) begin
state_before_fall <= LEFT;
end
else if (dig && (current_state==LEFT || current_state==RIGHT)) begin
state_before_fall <= current_state;
end
else begin
state_before_fall <= state_before_fall;
end
end
always @(*) begin
if (ground) begin
case (current_state)
LEFT: begin
if (dig) begin
next_state = DIGGING;
end
else if (bump_left) begin
next_state = RIGHT;
end
else begin
next_state = LEFT;
end
end
RIGHT: begin
if (dig) begin
next_state = DIGGING;
end
else if (bump_right) begin
next_state = LEFT;
end
else begin
next_state = RIGHT;
end
end
FALL: begin
next_state = state_before_fall;
end
DIGGING: begin
next_state = DIGGING;
end
default:
next_state <= LEFT;
endcase
end
else begin
next_state = FALL;
end
end
always @(posedge clk,posedge areset) begin
if (areset) begin
current_state <= LEFT;
end
else begin
current_state <= next_state;
end
end
always @ (posedge clk, posedge areset) begin
if (areset) begin
cnt <= 5'd0;
end
else if (next_state==FALL) begin
if (cnt==5'd21)
cnt <= cnt;
else
cnt <= cnt+5'd1;
end
else begin
cnt <= 5'd0;
end
end
always @(posedge clk, posedge areset) begin
if (areset)
splat_flag <= 1'b0;
else if (cnt==5'd21 && ground)
splat_flag <= 1'b1;
else
splat_flag <= splat_flag;
end
assign walk_left = splat_flag?1'b0:((current_state==LEFT)?1'b1:1'b0);
assign walk_right = splat_flag?1'b0:((current_state==RIGHT)?1'b1:1'b0);
assign aaah = splat_flag?1'b0:((current_state==FALL)?1'b1:1'b0);
assign digging = splat_flag?1'b0:((current_state==DIGGING)?1'b1:1'b0);
endmodule