【S002】round robin Verilog实现

目录

1.功能表述

2.仿真波形

3.功能代码

4.test beach

---

1.功能表述

找最末端bit=1的下标，难点：输出是连续的，不能中间不能隔拍。

    input        [NUM-1:0]  	 req,//15'b010_1000_1010_1100 //各个总线的请求
    input                        req_valid,//脉冲//标志输入有效
    output 	 [NUM_LOG-1:0]	 sel,//依次输出为1下标，选中某个总线//2 3 5 7 11 13 
    output			 sel_valid

2.仿真波形

3.功能代码

`timescale 100 ps / 1 ps
module round_robin #(
parameter NUM			=	4,
parameter NUM_LOG		=	2)
(
    input        				clk,
    input        				rst_n,
	
    input        [NUM-1:0]  	req,//1101100//各个总线的请求
    input                	 	req_valid,//脉冲//标志输入有效
	output 	     [NUM_LOG-1:0]	sel,//依次输出为1下标，选中某个总线
	output						sel_valid
);

reg [NUM-1:0]  	in_value;//存放被修改的
reg [NUM_LOG-1:0]	out_value;
always@(posedge clk or negedge rst_n)begin
	    if(rst_n == 1'b0)begin
		in_value <= #1 {NUM{1'b0}};
    end else if( req_valid ) begin//输入有效将入存下来//脉冲
		in_value <= #1 req;
    end else  begin//
		// in_value <= #1 in_value & (~( 16'b1<<(out_value+1)) );
		in_value <= #1 in_value & (~( 16'b1<<out_value) );
	end		
end
assign sel 		 = out_value;
assign sel_valid = out_value!= {NUM_LOG{1'b0}};

-----------用来搜索最低位1的位置（下标）,单独一部分------
// parameter NUM			=	4;
// parameter NUM_LOG		=	2;
integer i ;
// wire [NUM-1:0]  	in_value;//1101100
// wire [NUM_LOG-1:0]	out_value;
always@(*)begin
	out_value = {NUM_LOG{1'b0}};
	    if( in_value == {NUM{1'b0} })begin
			out_value = { NUM_LOG{1'b0} };
			i 		  = 0;
    end else begin
		for ( i=NUM-1 ; i>=0;i=i-1 ) begin
			if ( in_value[i] == 1'b1 )
				out_value = i[NUM_LOG-1:0];
		end
	end
end
	
endmodule

4.test beach

`timescale 100 ps / 1 ps
module tb();
	
parameter NUM		=15;
parameter NUM_LOG   =4;

    reg [NUM-1:0]  		req;
    reg 		  		req_valid;
    wire [NUM_LOG-1:0]  sel;
    wire 		  		sel_valid;
	reg clk,rst_n;
	
    round_robin # (
	.NUM(NUM),
	.NUM_LOG(NUM_LOG)		
	)
	round_robin_u (
	.clk    	(clk  ),
	.rst_n  	(rst_n),
	.req    	(req ),
	.req_valid  (req_valid),
	.sel    	(sel),
	.sel_valid  (sel_valid)
    );

    initial begin
	clk   = 1'b0;
	rst_n = 1'b0;
	req   = 1'b0;
	req_valid = 1'b0;
	#30ns;
	rst_n = 1'b1;
    end

    initial begin
	forever begin
	    #5ns;
	    clk = ~clk;
	end
    end
    initial begin
	#20ns;
	@(posedge clk) #1ns; req = 1'b0;
	@(posedge clk) #1ns; req_valid = 1'b0;
	
	#100//2 3 5 7 11 13 15
	@(posedge clk) #1ns; req = 15'b010_1000_1010_1100;req_valid = 1'b1;
	@(posedge clk) #1ns; req_valid = 1'b0;
    end
endmodule

仿真工程

https://www.jianguoyun.com/p/DczCmuUQupbwCBj9msID (访问密码 : csdn)